ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 81

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

LITE TIMER (Cont’d)
11.3.4 Low Power Modes
11.3.5 Interrupts
Note: The TBxF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generate an interrupt if the enable bit is set in
the LTCSR1 or LTCSR2 register and the interrupt
mask in the CC register is reset (RIM instruction).
11.3.6 Register Description
LITE TIMER CONTROL/STATUS REGISTER 2
(LTCSR2)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved, must be kept cleared.
Bit 1 = TB2IE Timebase 2 Interrupt enable
This bit is set and cleared by software.
0: Timebase (TB2) interrupt disabled
1: Timebase (TB2) interrupt enabled
Bit 0 = TB2F Timebase 2 Interrupt Flag
This bit is set by hardware and cleared by software
Mode
SLOW
WAIT
ACTIVE HALT No effect on Lite timer
HALT
Timebase 1
Event
Timebase 2
Event
IC Event
Interrupt
7
0
Event
0
Event
TB1F
TB2F
Flag
ICF
0
Description
No effect on Lite timer
(this peripheral is driven directly
by f
No effect on Lite timer
Lite timer stops counting
Control
Enable
TB1IE
TB2IE
OSC
ICIE
0
Bit
/32)
0
from
Wait
Exit
Yes
0
Active
from
Halt
Exit
Yes
No
No
TB2IE
from
Exit
Halt
No
TB2F
0
reading the LTCSR register. Writing to this bit has
no effect.
0: No Counter 2 overflow
1: A Counter 2 overflow has occurred
LITE
(LTARR)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = AR[7:0] Counter 2 Reload Value
These bits register is read/write by software. The
LTARR value is automatically loaded into Counter
2 (LTCNTR) when an overflow occurs.
LITE TIMER COUNTER 2 (LTCNTR)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:0 = CNT[7:0] Counter 2 Reload Value
This register is read by software. The LTARR val-
ue is automatically loaded into Counter 2 (LTCN-
TR) when an overflow occurs.
LITE TIMER CONTROL/STATUS REGISTER
(LTCSR1)
Read / Write
Reset Value: 0x00 0000 (x0h)
Bit 7 = ICIE Interrupt Enable
This bit is set and cleared by software.
0: Input Capture (IC) interrupt disabled
1: Input Capture (IC) interrupt enabled
CNT7
AR7
ICIE
7
7
7
CNT6
AR6
ICF
TIMER
CNT5
AR5
TB
AUTORELOAD
TB1IE
CNT4
AR4
CNT3
TB1F
AR3
CNT2
AR2
-
ST7LITE1xB
REGISTER
CNT1
AR1
-
81/159
CNT0
AR0
0
0
0
-
1