ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 87

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 55. Generic SS Timing Diagram
Figure 56. Hardware/Software Slave Select Management
– SS internal must be held high continuously
Figure
(if CPHA = 0)
(if CPHA = 1)
MOSI/MISO
Master SS
Slave SS
Slave SS
4).
SS external pin
SSI bit
Byte 1
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA = 1 (data latched on second clock edge):
If CPHA = 0 (data latched on first clock edge):
– SS internal must be held low during the entire
– SS internal must be held low during byte
Byte 2
SS internal
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM = 1 and
SSI = 0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
0.1.5.3).
3):
ST7LITE1xB
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