ST7LIT10BF1 STMicroelectronics, ST7LIT10BF1 Datasheet - Page 98

• Manufacturer Part Number: ST7LIT10BF1
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI
• Manufacturer: STMicroelectronics

Specifications of ST7LIT10BF1

• Up To 4 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection, In-circuit Programming And In-application Programming (icp And Iap). 10k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• 128 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55˚C.
• Clock Sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow

ST7LITE1xB
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription (ADCDRL register).
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
98/159
1
EOC SPEED ADON
7
Channel Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
0
CH2
0
0
0
0
1
1
1
CH2
CH1
CH1
0
0
1
1
0
0
1
CH0
CH0
0
1
0
1
0
1
0
0
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. It is advised
to use this bit to calibrate the ADC when amplifier
is ON. Setting this bit internally connects amplifier
input to 0V. Hence, corresponding ADC output can
be used in software to eliminate amplifier-offset er-
ror.
0: Calibration off
1: Calibration on. (The input voltage of the amplifi-
er is set to 0V)
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit in the ADCCSR regis-
ter to configure the ADC clock speed as shown on
the table below.
Note: max f
13.11 on page
D9
7
7
0
D8
0
ADC
D7
f
f
139)
0
f
CPU
CPU
f
ADC
CPU
allowed = 4MHz (see
/2
/4
AMP
CAL
D6
SLOW
D5
AMP-
SEL
D4
SLOW SPEED
0
0
1
D3
D1
section
D2
D0
0
1
x
0
0