ST6252C STMicroelectronics, ST6252C Datasheet
ST6252C
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ST6252C Summary of contents
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... Look-up table capability in Program Memory ■ Data storage in Program Memory: ■ User selectable size Data RAM: 128 bytes ■ Data EEPROM: 64 bytes (not in ST6252C devices) ■ User programmable options ■ 9 I/O pins, fully programmable as: ■ – Input with pull-up resistor – Input without pull-up resistor – ...
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... ST6252C ST6262B ST6262C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . 16 3.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 RESETS (CONT’ 3.4 DIGITAL WATCHDOG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4 ...
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... GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6252C and ST6262C devices are low cost members of the ST62xx 8-bit HCMOS family of mi- crocontrollers, which is targeted at low to medium complexity applications. All ST62xx devices are based on a building block approach: a common core is surrounded by a number of on-chip periph- erals ...
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... ST6252C ST6262B ST6262C 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are internally connected to the on-chip oscillator circuit. A quartz crystal, a ceramic resonator or an external clock signal can be connected between these two pins ...
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... MEMORY 0FF0h INTERRUPT & RESET VECTORS 0FFFh ST6252C ST6262B ST6262C Briefly, Program space contains user program code in OTP and user vectors; Data space con- tains user data in RAM and in OTP, and Stack space accommodates six levels of stack for sub- routine and interrupt service routine nesting. ...
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... ST6252C ST6262B ST6262C MEMORY MAP (Cont’d) 1.3.2 Program Space Program Space comprises the instructions to be executed, the data required for immediate ad- dressing mode instructions, the reserved factory test area and the user vectors. Program Space is addressed via the 12-bit Program Counter register (PC register) ...
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... AR TIMER STATUS/CONTROL REGISTER1 AR TIMER STATUS/CONTROL REGISTER2 WATCHDOG REGISTER AR TIMER RELOAD/CAPTURE REGISTER AR TIMER COMPARE REGISTER AR TIMER LOAD REGISTER EEPROM - bytes DATA RAM/EEPROM REGISTER EEPROM CONTROL REGISTER * WRITE ONLY REGISTER ST6252C ST6262B ST6262C X REGISTER Y REGISTER V REGISTER W REGISTER RESERVED RESERVED 0C8h* 0C9h* RESERVED RESERVED RESERVED ...
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... ST6252C ST6262B ST6262C MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ad- dress 0000h and 0FFFh (top memory address de- pends on the specific device) ...
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... E²PROM page (when available) when the parallel writing mode is set for the E²PROM, as defined in EECTL register. Table 3. Data RAM Bank Register Set-up DRBR 10h other ST6252C ST6262B ST6262C ST62T52C ST62T62C None None Not available EEPROM page 0 Not Available Not Available Not available Not available ...
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... ST6252C ST6262B ST6262C MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described in Table 4 . EEPROM locations are accessed di- rectly by addressing these paged sections of data space ...
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... E2ENA and E2PAR2 bits are also set. Notes: The EEPROM page shall not be changed through the DRBR register when the E2PAR2 bit is set. ST6252C ST6262B ST6262C EEPROM Control Register (EECTL) Address: EAh — Read/Write Reset status: 00h 7 ...
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... ST6252C ST6262B ST6262C 1.4 PROGRAMMING MODES 1.4.1 Option Bytes The two Option Bytes allow configuration capabili the MCUs. Option byte’s content is automati- cally read, and the selected options enabled, when the chip reset is activated. It can only be accessed during the programming mode. This access is made either automatically ...
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... EEPROM data pages are supplied in the virgin state FFh. Partial or total programming of EEP- ROM data memory can be performed either through the application software or through an ex- ST6252C ST6262B ST6262C ternal programmer. Any STMicroelectronics tool used for the program memory (OTP/EPROM) can also be used to program the EEPROM data mem- ory ...
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... ST6252C ST6262B ST6262C 2 CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals via internal address, data, and control buses. In-core communication is arranged as shown in Figure 6 ...
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... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or ST6252C ST6262B ST6262C a RETI instructions occurs. As the NMI mode is automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. ...
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... ST6252C ST6262B ST6262C 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor ( addition, a Low Frequency Auxiliary Os- ...
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... OSG and it should not be ena- bled in applications that use the SPI or the UART. It should also be noted that power consumption in Stop mode is higher when the OSG is enabled (around 50µA at nominal conditions and room temperature). ST6252C ST6262B ST6262C , is limited to INT Figure 12.. Figure 10 ...
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... ST6252C ST6262B ST6262C CLOCK SYSTEM (Cont’d) Figure 9. OSG Filtering Principle (1) (2) (3) (4) (1) Maximum Frequency for the device to work correctly (2) Actual Quartz Crystal Frequency at OSCin pin (3) Noise from OSCin (4) Resulting Internal Frequency Figure 10. OSG Emergency Oscillator Principle Main Oscillator Emergency Oscillator ...
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... When the OSG is enabled, access to this area is prevented. The internal frequency is kept When the OSG is disabled, operation in this area is not guaranteed When the OSG is enabled, access to this area is OSG Min. prevented. The internal frequency is kept at f ST6252C ST6262B ST6262C POR Core : 13 TIMER ...
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... ST6252C ST6262B ST6262C 3.2 RESETS The MCU can be reset in four ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. – by Low Voltage Detection (LVD) 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...
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... RESET 3.2.5 Application Notes No external resistor is required between V the Reset pin, thanks to the built-in pull-up device. ST6252C ST6262B ST6262C ues, allowing hysteresis effect. Reference value in case of voltage drop has been set lower than the reference value for power-on in order to avoid any parasitic Reset when MCU start's running and sinking current on the supply ...
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... ST6252C ST6262B ST6262C RESETS (Cont’d) 3.2.6 MCU Initialization Sequence When a reset occurs the stack is reset, the PC is loaded with the address of the Reset Vector (locat program ROM starting at address 0FFEh). A jump to the beginning of the user program must be coded at this address. Following a Reset, the In- terrupt flag is automatically set, so that the CPU is in Non Maskable Interrupt mode ...
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... FFh 0D2h 7Fh 0D8h FEh 0D1h 40h ST6252C ST6262B ST6262C Comment EEPROM enabled (if available) I/O are Input with pull-up I/O are Input with pull-up I/O are Input with pull-up Interrupt disabled TIMER disabled AR TIMER stopped As written if programmed Max count loaded ...
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... ST6252C ST6262B ST6262C 3.4 DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset by reloading the counter, and ...
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... MHz, this is equivalent to timer peri- ods ranging from 384 µs to 24.576 ms). Figure 17. Watchdog Counter Control (DWDR Figure 17.. D7 ST6252C ST6262B ST6262C C SR RESET OSC 12 VR02068A 25/75 ...
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... ST6252C ST6262B ST6262C DIGITAL WATCHDOG (Cont’d) 3.4.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110 Bit Watchdog Control bit If the hardware option is selected, this bit is forced high and the user cannot change it (the Watchdog is always active) ...
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... STOP/WAIT modes. Figure 19. Digital Watchdog Block Diagram RESET Q RSFF S R DB0 Figure 18. A typical circuit making use of the EXERNAL STOP MODE CONTROL feature SWITCH SET DB1.7 LOAD SET 8 WRITE RESET DATA BUS ST6252C ST6262B ST6262C NMI I/O VR02002 -12 OSCILLATOR CLOCK VA00010 27/75 ...
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... ST6252C ST6262B ST6262C 3.5 INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated interrupt service routine. These vectors are located in Pro- ...
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... The interrupt is serviced. – Return from interrupt (RETI) ST6252C ST6262B ST6262C MCU – Automatically the MCU switches back to the nor- mal flag set (or the interrupt flag set) and pops the previous PC value from the stack ...
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... ST6252C ST6262B ST6262C INTERRUPTS (Cont’d) 3.5.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed by single-bit operations. Address: 0C8h — Write Only ...
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... IOR REG. C8H, bit 6 FF CLK Q CLR I Start 2 IOR REG. C8H, bit 5 OVF OVIE CPF CPIE EF EIE TMZ ETI EOC EAI FF CLK Q CLR I Start 0 Bit GEN (IOR Register) ST6252C ST6262B ST6262C INT #1 (FF6,7) RESTART FROM STOP/WAIT INT #2 (FF4,5) INT #3 (FF2,3) INT #4 (FF0,1) NMI (FFC,D) VA0426K 31/75 ...
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... ST6252C ST6262B ST6262C 3.6 POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following paragraphs. 3.6.1 WAIT Mode The MCU goes into WAIT mode as soon as the WAIT instruction is executed ...
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... Nevertheless, two cases must be consid- ered: – If the interrupt is a normal one, the interrupt rou- tine in which the WAIT or STOP mode was en- ST6252C ST6262B ST6262C tered will be completed, starting with the execution of the instruction which follows the STOP or the WAIT instruction, and the MCU is still in the interrupt mode ...
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... ST6252C ST6262B ST6262C 4 ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with pull-up, but without interrupt – Analog input – ...
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... Mode Input With pull-up, no interrupt Input No pull-up, no interrupt Input With pull-up and with interrupt Input Analog input (when available) Output Open-drain output (20mA sink when available) Output Push-pull output (20mA sink when available) ST6252C ST6262B ST6262C Option 35/75 ...
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... ST6252C ST6262B ST6262C I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated in 23.. All other transitions are potentially risky and ...
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... PC2-PC3 5mA Open drain output PB0, PB2-PB3,PB6-PB7 30mA PA4-PA5 Push-pull output PC2-PC3 5mA Push-pull output PB0, PB2-PB3,PB6-PB7 30mA Note 1. Provided the correct configuration has been selected. (1) SCHEMATIC ST6252C ST6262B ST6262C Data in Interrupt Data in Interrupt Data in Interrupt ADC Data out Data out 37/75 ...
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... ST6252C ST6262B ST6262C I/O PORTS (Cont’d) 4.1.3 ARTimer alternate functions When bit PWMOE of register ARMC is low, pin ARTIMout/PB7 is configured as any standard pin of port B through the port registers. When PW- MOE is high, ARTMout/PB7 is the PWM output, in- dependently of the port registers configuration. Figure 24. Peripheral Interface Configuration of AR Timer ...
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... DATA BUS 8-BIT 5 COUNTER 4 SELECT ST6252C ST6262B ST6262C Table 13.), the clock input of the timer/coun- illustrates the Timer’s working principle STATUS/CONTROL REGISTER TMZ ETI D5 D4 PSI PS2 PS1 PS0 ) INT b0 INTERRUPT LINE ...
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... ST6252C ST6262B ST6262C TIMER (Cont’d) 4.2.1 Timer Operation The Timer prescaler is clocked by the prescaler clock input (f ÷ 12). INT The user can select the desired prescaler division ratio through the PS2, PS1, PS0 bits. When the TCR count reaches 0, it sets the TMZ bit in the TSCR ...
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... PS0 1 1 Timer Counter Register (TCR) Address: 0D3h — Read/Write 7 D7 Bit 7-0 = D7-D0: Counter Bits. Prescaler Register PSC Address: 0D2h — Read/Write 7 D7 Bit 7 = D7: Always read as "0". Bit 6-0 = D6-D0: Prescaler Bits. ST6252C ST6262B ST6262C PS1 PS0 ...
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... ST6252C ST6262B ST6262C 4.3 AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f external clock source. A Mode Control Register, ARMC, two Status Control Registers, ARSC0 and ...
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... CC0-CC1 PB6/ ARTIMin SL0-SL1 EF SYNCHRO DATA BUS 8 AR COMPARE REGISTER 8 COMPARE 8 8-Bit 7-Bit AR COUNTER RELOAD/CAPTURE REGISTER 8 DATA BUS ST6252C ST6262B ST6262C DDRB7 DRB7 CPF R S PWMOE OVF OVF OVIE LOAD TCLD EIE EF CPF CPIE 8 AR LOAD REGISTER 8 VR01660A PB7/ ARTIMout ...
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... ST6252C ST6262B ST6262C AUTO-RELOAD TIMER (Cont’d) It should be noted that the reload values will also affect the value and the resolution of the duty cycle of PWM output signal. To obtain a signal on ARTI- Mout, the contents of the ARCP register must be greater than the contents of the ARRC register. ...
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... ARRC register and setting the TLCD bit in the ARMC reg- ister. ST6252C ST6262B ST6262C Load on External Input. The counter operates as a free running 8-bit counter fed by the prescaler. the count is incremented on every clock rising edge ...
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... ST6252C ST6262B ST6262C AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: D5h — Read/Write Reset status: 00h 7 TCLD TEN PWMOE EIE CPIE The AR Mode Control Register ARMC is used to program the different operating modes of the AR Timer, to enable the clock and to initialize the counter ...
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... AR Compare Register. The CP compare register is used to hold the compare value for the compare function. AR Compare Register (ARCP) Address: DAh — Read/Write 7 D7 Bit 7-0 = D7-D0: Compare Data Bits. These are the Compare register data bits. Table Clock Source ST6252C ST6262B ST6262C ...
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... ST6252C ST6262B ST6262C 4.4 A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of 70us (at an oscillator clock frequency of 8MHz). The ADC converts the input voltage by a process ...
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... A/D converter if set to “1”. Writing a “0” to this bit will put the ADC in power down mode (idle mode). Bit 3-0 = D3-D0. Not used A/D Converter Data Register (ADR) Address: 0D0h — Read only 7 D7 Bit 7-0 = D7-D0: 8 Bit A/D Conversion Result. ST6252C ST6262B ST6262C EOC STA PDS ...
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... ST6252C ST6262B ST6262C 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 core has the ability to set or clear any register or RAM location bit of the Data space with a single instruction ...
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... One operand is the Accumulator for LOAD and the other operand is obtained from data memory using one of the addressing modes. For Load Immediate one operand can be any of the 256 data space bytes while the other is always immediate data. Addressing Mode Bytes ST6252C ST6262B ST6262C Cycles ...
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... ST6252C ST6262B ST6262C INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data space memory con- Table 17. Arithmetic & Logic Instructions ...
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... JP abc Extended Notes: abc. 12-bit address Not Affected ST6252C ST6262B ST6262C Control Instructions. The control instructions control the MCU operations during program exe- cution. Jump and Call. These two instructions are used to perform long (12-bit) jumps or subroutines call inside the whole program space. ...
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... ST6252C ST6262B ST6262C Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 JRNZ 4 CALL abc 0001 1 pcr 2 ext 1 2 JRNZ 4 CALL 2 ...
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... Indicates Illegal Instructions e 5 Bit Displacement b 3 Bit Address rr 1byte dataspace address nn 1 byte immediate data abc 12 bit address ee 8 bit Displacement ST6252C ST6262B ST6262C 1101 1110 1111 LDI 2 JRC 4 LD rr,nn e a,(y) imm 1 prc 1 ind DEC 2 JRC 4 LD ...
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... ST6252C ST6262B ST6262C 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V ...
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... Suffix 3. Suffix 3.0V, 1 & 6 Suffix 3. Suffix 4. & 6 Suffix 4. Suffix 4 4 & 6 Suffix version 3 Suffix version 1 & 6 Suffix version 3 3.6 4 4.5 SUPPLY VOLTAGE (V ST6252C ST6262B ST6262C Value Min. Typ. Max. - -40 125 3.0 6.0 3.0 6.0 3.6 6.0 4.5 6.0 3.0 6.0 3.0 6.0 4.0 6.0 4.5 6.0 0 4 ...
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... ST6252C ST6262B ST6262C 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys All Input pins V LVD Threshold in power- LVD threshold in powerdown dn Low Level Output Voltage ...
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... 3. 4. VDD=5.0V (Except 626xB ROM) R=47k R=100k R=470k VDD=5.0V (626xB ROM R=10k R=27k R=67k R=100k All Inputs Pins All Outputs Pins ST6252C ST6262B ST6262C Value Min. Typ. Max. V +50 mV 4.1 4.3 dn 3.6 3 0.1 0.8 1.2 0.1 0.8 1.3 2.0 4.9 3.5 10 Value Min. ...
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... ST6252C ST6262B ST6262C 6.5 A/D CONVERTER CHARACTERISTICS (T = -40 to +125°C unless otherwise specified) A Symbol Parameter Res Resolution (1) (2) A Total Accuracy TOT t Conversion Time C ZIR Zero Input Reading FSR Full Scale Reading Analog Input Current During AD I Conversion AC Analog Input Capacitance IN Notes: 1. Noise at VDD, VSS <10mV 2 ...
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... Figure 33. Vol versus Iol for High sink (30mA) I/Oports at T=25° This curves represents typical variations and is given for guidance only 20 30 Iol (mA Iol (mA Iol (mA) ST6252C ST6262B ST6262C T = -40° 25° 95° 125°C 40 Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V 40 Vdd = 3.0V Vdd = 4.0V Vdd = 5.0V Vdd = 6.0V 40 61/75 ...
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... ST6252C ST6262B ST6262C Figure 34. Vol versus Iol for High sink (30mA) I/O ports at Vdd= This curves represents typical variations and is given for guidance only Figure 35. Voh versus Ioh on all I/O port at 25° This curves represents typical variations and is given for guidance only Figure 36 ...
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... Mhz for OTP devices Vdd for OTP devices Vdd for ROM devices Vdd ST6252C ST6262B ST6262C T = -40° 25° 95° 125° -40° 25° 95° 125° -40° 25° 95° 125°C ...
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... ST6252C ST6262B ST6262C Figure 40. Idd WAIT versus V 2.5 2 1 This curves represents typical variations and is given for guidance only Figure 41. Idd RUN versus This curves represents typical variations and is given for guidance only Figure 42. LVD thresholds versus temperature 4 ...
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... Figure 44. RC frequency versus 0.1 3 This curves represents typical variations and is given for guidance only for ROM ST626xB only VDD (volts)] (Except for ST626xB ROM devices) DD 3.5 4 4.5 5 VDD (volts) ST6252C ST6262B ST6262C R=1OK R=27K R=67K R=100K 6 R=47K R=100K R=470K 5.5 6 65/75 ...
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... ST6252C ST6262B ST6262C 7 PACKAGE MECHANICAL DATA In order to meet environmental requirements, ST offers these devices in different grades of ECO- ® PACK packages, depending on their level of en- vironmental compliance. ECOPACK Figure 45. 16-Pin Plastic Dual In-Line Package, 300-mil Width Figure 46. 16-Pin Ceramic Side-Brazed Dual In-Line Package ...
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... PACKAGE MECHANICAL DATA (Cont’d) Figure 47. 16-Pin Plastic Small Outline Package, 300-mil Width Figure 48. 16-Pin Plastic Shrink Small Outline Package 45× ST6252C ST6262B ST6262C mm Dim. Min Typ Max Min A 2.35 2.65 0.093 C A1 0.10 0.30 0.004 B 0.33 0.51 0.013 C 0.23 0.32 0.009 D 10.10 10.50 0.398 E 7 ...
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... ST6252C ST6262B ST6262C THERMAL CHARACTERISTICS Symbol Parameter RthJA Thermal Resistance 68/75 Test Conditions Min. PDIP16 PSO16 Value Unit Typ. Max. 55 °C/W 75 ...
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... None 64 None 64 They offer the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version. ST6252C ST6262B ST6262C Temperature range 0 to +70°C - 85°C - 125°C - 85°C - 125°C - 85°C - 125° ...
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... ST6252C ST6262B ST6262C The following section deals with the procedure for transfer of customer codes to STMicroelectronics. 8.2.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected FASTROM options. The ROM contents are to be sent on diskette electronic means, with the hexadecimal file generated by the development tool ...
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... Bytes ST6262BM3/XXX ST6262BN1/XXX ST6262BN6/XXX ST6262BN3/XXX The ST6252C and ST6262B are mask pro- grammed ROM versions of ST62T52C and ST62T62C OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version, except the LVD & ...
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... STMicroelectronics. The signed listing forms a part of the contractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. Table 26. ROM Memory Map for ST6252C/62B Device Address PROTECT 0000h-087Fh 0880h-0F9Fh 14V 0FA0h-0FEFh ...
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... ST6252C (2 KB ST6262B (2 KB) ...
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... ST6252C ST6262B ST6262C 9 REVISION HISTORY Table 27. Document revision history Date Rev. Modification of “Additional Notes for EEPROM Parallel Mode” (p.13) Changed f In section 4.2 on page 41: vector #4 instead of vector #3 for the timer interrupt request. Jul-2001 2.9 Changed Figure 43 Changed Figure 45. Changed option list on Swapped D11 and D10 description on ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America Please Read Carefully: © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST6252C ST6262B ST6262C 75/75 ...