VIPER15

Manufacturer Part NumberVIPER15
DescriptionVIPerPlus family: quasi-resonant high performance off line high voltage converter
ManufacturerSTMicroelectronics
VIPER15 datasheet
 


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VIPER15
The time, from the high load detection, V
depends from the value of the capacitor C
OLP delay time can be calculating by the formula:
Equation 8
The current, I
FB,
also a part of the compensation loop , so they have to be selected taking into account the
proper delay and loop stability consideration. The
page 30
show two different feedback networks.
In the
Figure 33 on page 27
circuit to compensate the feedback loop but also as element to delay the OLP shut down
owing to the time needed to charge the capacitor (see the
After the start-up time, t
capacitor could not be at its nominal value and the controller interpreter this situation as an
overload condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start-up. See the relevant
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the overload condition only when the output voltage
is in steady state. The output transient time depends from the value of the output capacitor
and from the load.
When the value of the C
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in
Figure 35 on page 30
Using this alternative compensation network, two poles (f
introduced by the capacitors C
The capacitor C
FB
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in
Figure 35 on page 30
Equation 9
Equation 10
= V
FB
and from the internal charge current, I
FB
T
=
C
OLP delay
FB
is 3 μA as minimum value. The components connected to the FB pin are
, the capacitor, C
FB
, during which the feedback voltage is fixed at V
SU
Section 7.3 on page 16
capacitor calculated for the loop stability is too low and cannot
FB
.
and C
and the resistor R
FB
FB1
introduces a pole (f
) at higher frequency than f
PFB
are reported by the equations below:
=
f
ZFB
⋅ π
2
C
R
=
FB
(
DYN
f
PFB
⋅ π
2
C
FB
Doc ID 15455 Rev 5
Operation description
, to the overload turn-off, V
FBlin
V
V
FBolp
FBlin
×
--------------------------------------- -
3μA
Figure 34 on page 30
and
Figure 35 on
, connected to FB pin is used as part of the
Equation 8
).
FBlin
.
, f
) and one zero (f
PFB
PFB1
.
FB1
and f
ZB
PFB1
1
R
FB
1
FB
1
+
R
)
FB
1
(
)
R
R
FB
(
DYN
)
FB
1
= V
,
FB
FBolp
. The
FB
, the output
) are
ZFB
. This pole
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