VIPER17 STMicroelectronics, VIPER17 Datasheet - Page 21

• Manufacturer Part Number: VIPER17
• Description: VIPerPlus family: fixed frequancy high performance off line high voltage converter
• Manufacturer: STMicroelectronics

VIPER17
When the feedback pin voltage reaches the threshold V
starts to charge the feedback capacitor (C
V
value of I
During the first start up phase of the converter, after the soft-start up time, t
voltage could force the feedback pin voltage to rise up to the
off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The
on page 22
The time from the over load detection (V
(V
using the formula:
Equation 5
In the
compensate the feedback loop but also as element to delay the OLP shut down owing to the
time needed to charge the capacitor (see equation 5).
After the start up time, t
capacitor could not be at its nominal value and the controller interpreter this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start up.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the C
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in
Using this alternative compensation network, two poles (f
introduced by the capacitors C
The capacitor C
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in
Equation 6
FBolp
FB
Figure 29
=
threshold, the converter is turned off and the start up phase is activated with reduced
Figure
V
FBolp
DDch
Figure 29 on page
and
are reported by the equations below:
) can be calculating by C
28, the capacitor connected to FB pin (C
to 0.6 mA. See
FB
Figure 29
introduces a pole (f
SS
FB
, during which the feedback voltage is fixed at
show the two different feedback networks.
capacitor calculated for the loop stability is too low and cannot
T
22.
Table 7 on page
OLP delay
Doc ID 14419 Rev 7
FB
and C
–
f
ZFB
FB
PFB
=
FB1
FB
value (see
=
2
) at higher frequency than f
FB
C
⋅
=
and the resistor R
⋅ π
) and when the feedback voltage reaches the
FB
V
C
6.
FBlin
×
FB
1
V
--------------------------------------- -
1
FBolp
) to the device shutdown
⋅
Figure 28 on page 22
R
FB
3μA
FB
1
–
FBlin
) is used as part of the circuit to
V
PFB
FBlin
an internal current generator
, f
V
FB1
PFB1
FBolp
.
) and one zero (f
Operation descriptions
threshold that switches
ZB
and f
V
FBlin
and
SS
PFB1
, the output
, the output
Figure
. This pole
Figure 28
ZFB
29),
) are
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