PM6681A STMicroelectronics, PM6681A Datasheet
PM6681A
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PM6681A Summary of contents
Page 1
... DC voltage error due to the output ripple. Pulse skipping technique increases efficiency at very light load. Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues. The PM6681A provides a selectable switching frequency, allowing three different values of switching frequencies for the two switching sections. The output voltages OUT1 and OUT2 can be adjusted from 0 ...
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... Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 20 7.4 Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5 No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.8 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.9 Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.10 Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28 8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.3 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.4 Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/47 PM6681A ...
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... PM6681A 9 Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.4 Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.5 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.6 Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.7 Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.8 Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6 9.8.7 9.8.8 10 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Input capacitor ...
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... Simplified application schematic 1 Simplified application schematic Figure 1. Application schematic 4/47 PM6681A ...
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... PM6681A 2 Pin settings 2.1 Connections Figure 2. Pin connection (top view) SGND COMP2 FSEL EN2 SHDN FB2 LDO OUT2 2.2 Functions Table 2. Pin functions N° Pin 1 SGND 2 COMP2 3 FSEL Signal ground ...
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... If V5SW is connected to OUT5 ( external 5 V supply) and V5SW is greater than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is directly connected to OUT5 through (max) switch. If V5SW is connected to GND, the LDO5 linear regulator is always on if the device is not in shutdown mode. PM6681A Function ...
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... PM6681A Table 2. Pin functions (continued) N° Pin 18 LDO5 19 VIN 20 CSENSE1 21 PHASE1 22 HGATE1 23 BOOT1 24 SKIP 25 EN1 26 PGOOD1 27 PGOOD2 28 FB1 29 OUT1 30 COMP1 31 VCC 32 VREF 5 V internal regulator output. It can provide up to 100 mA peak current. LDO5 pin supplies embedded low side gate drivers and an external load. ...
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... Functional block diagram 3 Functional block diagram Figure 3. Functional block diagram 8/47 PM6681A ...
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... PM6681A 4 Maximum ratings Table 3. Absolute maximum ratings V5SW, LDO5 to PGND VIN to PGND HGATEx and BOOTx, to PHASEx PHASEx to PGND CSENSEx, to PGND CSENSEx to BOOTx LGATEx to PGND FBx, COMPx, SKIP, FSEL,VREF to SGND, LDO FB PGND to SGND SHDN, PGOODx, OUTx, VCC, ENx to SGND Power dissipation at T Maximum withstanding voltage range test condition: CDF-AEC-Q100-002- “ ...
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... Fixed negative current limit threshold 10/47 Test condition V5SW > 4.9 V FBx > VREF, Vref in regulation, V5WS SHDN connected to GND ENx to GND, V5SW to GND ( CSENSE PGND PGND PHASE PGND PHASE PM6681A Min Typ Max Unit 4.8 4.9 V 4.6 4. Ω 1.8 3 Ω 0.2 0.35 ...
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... PM6681A Table 6. Electrical characteristics ( °C, unless otherwise specified) (continued Symbol Parameter On time pulse width On time duration_ Ton @VIN = 24 V OFF time Minimum off time T OFFMIN @VIN = 24 V Voltage reference V Voltage accuracy REF Load regulation Undervoltage lockout fault threshold ...
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... V PGOOD1 Sink (1) (1) (1) Low level (1) Middle level (1) High level (1) (1) ( EN1 SKIP SHDN FSEL PM6681A Min Typ Max Unit 170 220 270 mA 0.1 µA 2.0 3 1.6 2.7 Ω 1.4 2.1 0.8 1.2 112 116 120 % 107 ...
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... PM6681A 6 Typical operating characteristics (FSEL = GND (200/300 kHz), SKIP = GND (skip mode), V5SW = EXT5 V (external 5 V power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high, OUT1 = 3.3 V, OUT2 = 1 load, LDO = 3.3 V, (LDO_FB divider = 5.6 k and 15 k) unless specified) Figure 4. Efficiency vs current load Figure 6 ...
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... Typical operating characteristics Figure 10. Standby mode input battery current vs input voltage Figure 12. OUT1 = 3.3 V switching frequency Figure 14. OUT1 = 3.3 V load regulation Figure 15. OUT2 = 1.8 V load regulation 14/47 Figure 11. Voltage reference vs load current \ Figure 13. OUT2 = 1.8 V switching frequency \ \ PM6681A ...
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... PM6681A Figure 16. LDO5 vs output current Figure 18. SHDN, OUT1, LDO and LDO5 power-up Figure 20. OUT1 = 3.3 V load transient Typical operating characteristics Figure 17. LDO vs output current \ Figure 19. OUT1, OUT2, LDO and LDO5 power-up \ Figure 21. OUT2 = 1.8 V load transient 15/47 ...
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... Typical operating characteristics Figure 22. 3.3 V soft-start (1 Ω load) Figure 24. OUT1 = 3.3 V soft-end (no load) Figure 26. OUT1 = 3.3 V soft-end (0.8 Ω load) 16/47 Figure 23. 1.8 V soft-start (0.6 Ω load) \ Figure 25. OUT2 = 1.8 V soft-end (no load) \ Figure 27. OUT2 = 1.8 V soft-end (0.6 Ω load) \ PM6681A ...
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... PM6681A Figure 28. 3.3 V no-audible skip mode Typical operating characteristics Figure 29. 1.8 V no-audible skip mode \ 17/47 ...
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... OUT2. The switching frequency of the two sections can be adjusted to three different values. In order to maximize the efficiency at light load condition, a pulse skipping mode can be selected. The PM6681A includes also linear regulator (LDO5) that can power the switching drivers. If the output OUT1 regulates order to maximize the efficiency in higher consumption status, the linear regulator can be turned off and their outputs can be supplied directly from the switching outputs ...
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... PM6681A Figure 30. Constant on time PWM control The duty cycle of the buck converter in steady state is: Equation 2 The PWM control works at a nearly fixed frequency f Equation 3 As mentioned the steady state switching frequency is theoretically independent from battery voltage and from output voltage. Actually the frequency depends on parasitic voltage drops that are present during the charging path (high side switch resistance, inductor resistance (DCR) and discharging path (low side switch resistance, DCR) ...
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... A minimum on-time (130 ns) is also introduced to assure the start-up switching sequence. PM6681A has a one-shot generator for each power section that turns on the high side MOSFET when the following conditions are satisfied simultaneously: the PWM comparator is high, the synchronous rectifier current is below the current limit threshold, and the minimum off-time has timed out ...
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... PM6681A Figure 32. Circuitry for output ripple compensation The integrator amplifier generates a current, proportional to the DC errors between the FB voltage and Vr, which decreases the output voltage in order to compensate the total static error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for the output ripple ...
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... At light load condition, If there is not a new switching cycle within a 30 µs (typ.) period, a no-audible skip mode cycle begins. Figure 34. No audible skip mode Inductor current 0 22/ ILOAD ( SKIP ) No audible skip mode ∼30us Low side − V × IN OUT T ON × Time PM6681A ...
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... PM6681A The low side switch is turned on until the output voltage crosses about Vreg+1 %. Then the high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is enabled until the inductor current reaches the zero-crossing threshold. This keeps the switching frequency higher than 33 kHz consequence of the control, the regulated voltage can be slightly higher than Vreg ( ...
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... Where R is the sensing element (R SNS PM6681A provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in PWM mode. This negative current limit threshold is measured between PHASE and SGND pins, comparing the magnitude drop on the PHASE node during the conduction time of the low side MOSFET with an internal fixed voltage of 120 mV ...
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... PM6681A 7.7 soft-start and soft-end Each switching section is enabled separately by asserting high EN1/EN2 pins respectively. In order to realize the soft-start, at the startup the overcurrent threshold is set the nominal value and the undervoltage protection (see related sections) is disabled. The controller starts charging the output capacitor working in current limit. The overcurrent threshold is increased from 100 % of the nominal value with steps every 700 µ ...
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... Internal linear regulators The PM6681A has two linear regulators providing respectively 5 V (LDO5) and an adjustable voltage (LDO) at ± accuracy. High side drivers, low side drivers and MOSFETs of internal circuitry are supplied by LDO5 output through VCC pin (an external RC filter may be applied between LDO5 and VCC) ...
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... PM6681A Table 8. V5SW multifunction pin V5SW GND The 5 V linear regulator is always turned on and supplies LDO5 output. Switching 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and output LDO5 output is supplied by the switching 5 V output. External 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and supply LDO5 output is supplied by the external 5 V ...
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... SHDN pin is high Shutdown SHDN is low 28/47 Conditions Switching regulators are enabled; internal linear regulators outputs are enabled. Internal linear regulators active (LDO5 is always on). In Standby mode LGATE1/LGATE2 pins are forced high while HGATE1/HGATE2 pins are forced low. All circuits off. PM6681A Description ...
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... Thermal protection The PM6681A has a thermal protection to preserve the device from overheating. The thermal shutdown occurs when the die temperature goes above +150 °C. In this case all internal circuitry is turned off and the power sections are turned off after the discharge mode ...
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... L(max) 30/47 to the AC adapter voltage, V INmax − × IN OUT L × ∆ the input voltage (max)) LRMS LOAD . LOAD(max) . The maximum ∆I LOAD(max) V OUT the output voltage and OUT : LRMS ∆ (max PM6681A . L L ...
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... PM6681A Equation 15 If hard saturation inductors are used, the inductor saturation current should be much greater than the maximum inductor peak current I Equation 16 Using soft saturation inductors it's possible to choose inductors with saturation current limit nearly Below there is a list of some inductor manufacturers. ...
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... CinRMS Series Capacitor value (uF) UMK432 X5506MM-T C3225X5R1E106M = P P DHighSide conduction Rated voltage (V) ESR max (mΩ) 2 6.3 + × × − Rated voltage ( must be higher than V DSS INmax + P switching PM6681A ...
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... PM6681A Maximum conduction losses are approximately: Equation 20 where R is the drain-source on resistance of the high side MOSFET. Switching losses DS(on) are approximately: Equation switching where ton and toff are the switching times of the turn off and turn off phases of the MOSFET. As general rule, high side MOSFETs with low gate charge are recommended, in order to minimize driver losses ...
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... STS25NH3LL 3.5 Type R (mΩ) DS(on) STS8DNH3LL 25 STS4DNF60L 65 Forward voltage Series (V) STPS1L30M 0.34 STPS1L20M 0.37 C RSS Rated reverse voltage ( 0.047 30 0.011 30 Gate charge (nC) Rated reverse voltage ( minimum INmax Rated reverse voltage Reverse current ( Figure usually enough to PM6681A (uA) 0.00039 0.000075 ...
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... PM6681A Figure 39. Circuitry for output ripple compensation The stability of the system depends firstly on the output capacitor zero frequency. The following condition should be satisfied: Equation 24 where design parameter greater than 3 and R determinates the minimum integrator capacitor value C Equation 25 where µs is the integrator trans conductance. ...
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... CUT C INT , C ), the ripple voltage at the COMP pin is given by: INT filt C = × INT V V RIPPLE RIPPLEout + INT C INT Figure − RIPPLE R ESR ∆ × C INT filt + C filt = × RIPPLEout C filt . given by: ESR R out PM6681A ...
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... PM6681A where ∆I is the inductor current ripple and VRIPPLE is the overall ripple of the T node L voltage. It should be chosen higher than approximately 30 mV. The new closed loop gain depends on C that: Equation 30 Where: Equation 31 where R is the sum of the ESR of the output capacitor Rout and the equivalent ESR ...
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... L = 2.5 µH, Cout = 330 µF with Rout = equations 31, 34 and C INT ⎞ 1 ⎟ ⎟ π × f ⎠ π × ≈ 12 mΩ. We design = 47 pF, R filt INT PM6681A = 1 kΩ by ...
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... PM6681A Typical components values are Ω and µF. ● VREF capacitor 100 nF ceramic capacitor on V ensure noise rejection. LDO5 output capacitors. Bypass the output of each linear regulator with 1 µF ceramic ● capacitor closer to the LDO pin and a 4.7 µF tantalum capacitor (ESR = 2 Ω). In most applicative conditions a 4.7 µ ...
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... V. IN ∆ = − I (min) I (max) Lvalley LOAD . ≡ ⋅ CSENSE µ 100 ° max ∆ = − I (min) I (max) Lvalley LOAD ≈ µ (min Ω ≈ Ω m 670 calculation) DS(on) I (min PM6681A ...
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... PM6681A (Let's assume T max 9.8.5 Input capacitor Maximum input capacitor RMS current is about 1.1 A. Then I We can put two 10 µF ceramic capacitors with I 9.8.6 Synchronous rectifier OUT1: Schottky diode STPS1L40M OUT2: Schottky diode STPS1L40M 9.8.7 Integrator loop (Refer to Figure 40 OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required. ...
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... Layout guidelines The layout is very important in terms of efficiency, stability and noise of the system possible to refer to the PM6681A demonstration board for a complete layout example. For good PC board layout follows these guidelines: ● Place on the top side all the power components (inductors, input and output capacitors, MOSFETs and diodes) ...
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... PM6681A ● As general rule, make the high side and low side drivers traces wide and short. The high side driver is powered by the bootstrap circuit. It's very important to place capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for example on the layer opposite to the device). Route HGATE and PHASE traces as near as possible in order to minimize the area between them ...
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... VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead. Very thin 1.00 mm Max. 2. Dimensions D2 and E2 are not in accordance with JEDEC. 44/47 Min 0.8 0 0.18 4.85 See exposed pad variations 4.85 See exposed pad variations 0.3 (1)(2) D2 Typ Max 3.10 3.20 Databook (mm) Typ Max 0.9 1 0.02 0.05 0.2 0.25 0.3 5 5.15 (2) 5 5.15 (2) 0.5 0.4 0.5 0.05 E2 Min Typ 2.90 3.10 PM6681A ® Max 3.20 ...
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... PM6681A Figure 45. Package dimensions Package mechanical data 45/47 ...
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... Revision history 12 Revision history Table 20. Document revision history Date 02-Nov-2006 03-Jun-2008 26-Jun-2008 46/47 Revision 1 Initial release Document status promoted from Target specification to 2 Datasheet Updated: Figure 1 on page 3 and Figure 17 on page 15 PM6681A Changes 4, Figure 27 on page 16, Figure 16 ...
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... PM6681A Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...