DS2433 Maxim, DS2433 Datasheet
DS2433
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DS2433 Summary of contents
Page 1
... Directly Connects to a Single Port Pin of a Microprocessor and Communicates 16.3kbps Overdrive Mode Boosts Communication Speed to 142kbps 8-Bit Family Code Specifies DS2433 Communication Requirements to Reader Presence Detector Acknowledges When Reader First Applies Voltage Low-Cost PR-35, SFN, Flip Chip, or 8-Pin SO Surface-Mount Packages ...
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... This process insures data integrity when modifying the memory. The 64-bit registration number provides a guaranteed unique identity which allows for absolute traceability and acts as node address if multiple DS2433s are connected in parallel to form a local network. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return. The PR-35 and SO packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring ...
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... Figure 1. DS2433 BLOCK DIAGRAM 64-BIT LASERED ROM Each DS2433 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See Figure 3 ...
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... TA1, TA2 and E/S. The master may obtain the contents of these registers by reading the scratchpad or derive it from the target address and the amount of data to be written. As soon as the DS2433 has received these bytes correctly, it will copy the data to the requested location beginning at the target address. ...
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... STAGE STAGE STAGE STAGE 48-BIT SERIAL NUMBER Polynomial = STAGE 8-BIT FAMILY CODE (23h) LSB MSB STAGE STAGE STAGE INPUT DATA DS2433 LSB LSB 8 ...
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... CRC generated by the DS2433. The memory address range of the DS2433 is 0000h to 01FFh. If the bus master sends a target address higher than this, the internal circuitry of the chip will set the seven most significant address bits to zero as they are shifted into the internal address register ...
Page 7
... The ending offset/data status byte is unaffected. The hardware of the DS2433 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers recommended to packetize data into data packets of the size of one memory page each ...
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... Figure 7. MEMORY FUNCTION FLOWCHART DS2433 ...
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... Figure 7. MEMORY FUNCTION FLOWCHART (continued DS2433 ...
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... Wait 5ms Reset Reset Pulse Presence Presence Pulse CCh Issue Skip ROM Command F0h Issue Read Memory command 00h TA1, beginning offset = 0 00h TA2, address = 0000h Read entire memory Reset Reset Pulse Presence Presence Pulse, done COMMENTS AUTHORIZATION CODE DS2433 ...
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... To facilitate this, each device attached to the 1-Wire bus must have open drain or 3-state outputs. The 1-Wire port of the DS2433 is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At regular speed the 1-Wire bus has a maximum data rate of 16.3kbps. The speed can be boosted to 142kbps by activating the Overdrive Mode. The 1-Wire bus requires a pullup resistor of approximately 5k ...
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... Reset Pulse transmitted by the bus master followed by Presence Pulse(s) transmitted by the slave(s). The Presence Pulse lets the bus master know that the DS2433 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the six ROM function commands ...
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... The Overdrive Match ROM command, followed by a 64-bit ROM sequence transmitted at Overdrive Speed, allows the bus master to address a specific DS2433 on a multidrop bus and to simultaneously set it in Overdrive Mode. Only the DS2433 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command ...
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... Figure 9. ROM FUNCTIONS FLOWCHART (FIRST PART DS2433 ...
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... Figure 9. ROM FUNCTIONS FLOWCHART (SECOND PART DS2433 ...
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... DS2433. During write time slots, the delay circuit determines when the DS2433 will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS2433 will hold the data line low overriding the 1 generated by the master. If the data bit is a “ ...
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... Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSES *IN ORDER NOT TO MASK INTERRUPT SIGNALLING BY OTHER DEVICES ON THE 1-WIRE BUS, t **INCLUDES RECOVERY TIME SHOULD ALWAYS BE LESS THAN 960µs. RSTL DS2433 ...
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... Figure 11. READ/WRITE TIMING DIAGRAM DS2433 ...
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... ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2433 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial ...
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... LOW0 t 1 LOWR t 15 RDV RELEASE REC t 480 RSTH t 480 RSTL t 15 PDHIGH t 60 PDLOW DS2433 (T = -40°C to +85°C.) A MAX UNITS NOTES A 4 +25°C) A MAX UNITS NOTES 800 5.0V +25 ...
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... PUP normal communications. 7) During the execution of the Copy Scratchpad command the DS2433 automatically erases the memory locations to be written to. No extra steps need to be taken by the bus master. 8) The duration of the low pulse sent by the master should be a minimum of 1μs with a maximum value ...
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... PACKAGE CODE 6 Flip Chip 3 PR-35 2 SFN 8 SO (208 mils) REFER TO OUTLINE NO. BF623#3 21-0291 D3+1 21-0247 G266N+1 21-0390 W8+2 21-0262 DS2433 2433 yywwrr ### FLIP CHIP (TOP VIEW WITH LASER MARK, CONTACTS NOT VISIBLE.) “yywwrr” = DATE/REVISION ###xx = LOT NUMBER LAND PATTERN NO. See 21-0291 — ...
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... The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DESCRIPTION from EC-table header to PUP from 0.8V to 0.5V, deleted V ILMAX © 2010 Maxim Integrated Products DS2433 PAGES CHANGED ...