DS24B33 Maxim, DS24B33 Datasheet
DS24B33
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DS24B33 Summary of contents
Page 1
... Each device has its own unalterable and unique 64-bit regis- tration number that is factory programmed into the chip. The registration number is used to address the device in a multidrop 1-Wire net environment. The DS24B33 is software compatible to the DS2433. Storage of Calibration Constants Board Identification ...
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... Storage Temperature Range .............................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Note 12: The I-V characteristic is linear for voltages less than +1V. Note 13: Applies to a single DS24B33 attached to a 1-Wire line. Note 14: Defines maximum possible bit rate. Equal to 1/(t Note 15: Interval after t during which a bus master is guaranteed to sample a logic there is a DS24B33 present. RSTL Minimum limit maximum limit is t PDHMAX Note 16: ε ...
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... SIDE VIEW GND N.C. 3 TO-92 4 _______________________________________________________________________________________ increases. A increases. A TOP VIEW + N.C. 1 N.C. 2 DS24B33 IO 3 GND 4 SO (208 mils) FRONT VIEW FRONT VIEW (T&R VERSION Pin Configurations 8 N. ...
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... The registration number guarantees unique identification and is used to address the device in a multidrop 1-Wire net environ- ment. Multiple DS24B33 devices can reside on a com- mon 1-Wire bus and be operated independently of each other. Applications of the DS24B33 include cali- bration data storage, PCB identification, and storage of product revision status ...
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... IO input is high. IO pro- vides sufficient power as long as the specified timing and voltage requirements are met. Each DS24B33 contains a unique registration number that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits ...
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... Figure 5. Memory Map _______________________________________________________________________________________ 1-Wire 4Kb EEPROM The DS24B33 EEPROM array (Figure 5) consists of 16 pages of 32 bytes each, starting at address 0000h and ending at address 01FFh. In addition to the EEPROM, the device has a 32-byte volatile scratchpad. Writes to the EEPROM array are a two-step process. First, data is written to the scratchpad and then copied into the main array ...
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... Writing data to the scratchpad clears this flag. Writing with Verification To write data to the DS24B33, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad ...
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... CRC generated by the DS24B33. The DS24B33’s memory address range is 0000h to 01FFh. If the bus master sends a target address higher than this, the DS24B33’s internal circuitry sets the 7 most significant address bits to zero as they are shifted into the internal address register. The Read Scratchpad command reveals the modified target address ...
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... DS24B33 DS24B33 SETS (E[4:0]) = INCREMENTS SCRATCHPAD OFFSET SCRATCHPAD OFFSET MASTER Tx RESET SCRATCHPAD OFFSET = 11111b? Y DS24B33 Tx CRC-16 OF COMMAND, ADDRESS, AND DATA BYTES AS THEY WERE SENT BY THE BUS MASTER N BUS MASTER MASTER Tx RESET? Rx "1" ROM FUNCTIONS FLOWCHART (FIGURE 9) Figure 7a. Memory Function Flowchart ...
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... BUS MASTER MASTER Tx RESET? Rx "1"s Y FOR POWER. PROG F0h N READ MEMORY? Y BUS MASTER Tx TA1 (T[7:0]), TA2 (T[15:8]) BUS MASTER Rx "1"s N MASTER Tx RESET? Y DS24B33 SETS MEMORY ADDRESS = (T[15:0]) BUS MASTER Rx DATA BYTE FROM MEMORY ADDRESS Y MASTER Tx RESET ADDRESS < 1FFh MASTER Tx RESET ...
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... The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS24B33 is a slave device. The bus master is typically a microcon- troller. The discussion of this bus system is broken down into three topics: hardware configuration, trans- action sequence, and 1-Wire signaling (signal types and timing) ...
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... The presence pulse lets the bus master know that the DS24B33 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM Function Commands ...
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... ROM code. Unlike the normal Skip ROM command, the Overdrive-Skip ROM command sets the DS24B33 in the overdrive mode (OD = 1). All communication following this command must occur at overdrive speed until a reset pulse of minimum 480µ ...
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... COMMAND DS24B33 Tx BIT 0 MASTER Tx BIT 0 DS24B33 Tx BIT 0 MASTER Tx BIT BIT 0 MATCH? BIT 0 MATCH DS24B33 Tx BIT 1 MASTER Tx BIT 1 DS24B33 Tx BIT 1 MASTER Tx BIT BIT 1 MATCH? BIT 1 MATCH DS24B33 Tx BIT 63 MASTER Tx BIT 63 DS24B33 Tx BIT 63 MASTER Tx BIT ...
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EEPROM TO FIGURE 9a FROM FIGURE 9a FROM FIGURE 9a TO FIGURE 9a NOTE: THE OD FLAG REMAINS THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED. Figure 9b. ROM ...
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... Figure 10 shows the initialization sequence required to begin any communication with the DS24B33. A reset pulse followed by a presence pulse indicates that the DS24B33 is ready to receive data, given the correct ROM and memory function command. If the bus master uses slew-rate control on the falling edge, it must pull ...
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... READ-DATA TIME SLOT PUP V IHMASTER ILMAX RESISTOR Figure 11. Read/Write Timing Diagrams 18 ______________________________________________________________________________________ dur- old has been crossed, the DS24B33 needs a recovery ILMAX thresh- time t TH REC ε t SLOT MASTER t W0L t SLOT MASTER t MSR MASTER SAMPLING WINDOW δ ...
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... When responding with a 1, the DS24B33 does not hold the data line low at all, and the voltage starts rising as soon δ ...
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EEPROM 1ST 2ND STAGE STAGE 9TH 10TH 11TH STAGE STAGE STAGE Figure 13. CRC-16 Hardware Description and Polynomial Command-Specific 1-Wire Communication Protocol—Legend SYMBOL RST 1-Wire reset pulse generated ...
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... EOM> For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status ...
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... Implemented text changes to better market the document Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...