DS2502 Maxim, DS2502 Datasheet

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DS2502

Manufacturer Part Number
DS2502
Description
The DS2502 1Kb Add-Only Memory identifies and stores relevant information about the product to which it is associated
Manufacturer
Maxim
Datasheet

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FEATURES
 1024 bits Electrically Programmable Read
 Unique, factory-lasered and tested 64-bit
 Built-in multidrop controller ensures
 EPROM partitioned into four 256-bit pages
 Each memory page can be permanently
 Device is an “add only” memory where
 Architecture allows software to patch data by
 Reduces control, address, data, power, and
 Directly connects to a single port pin of a
 8-bit family code specifies DS2502
 Presence detector acknowledges when the
 Low cost TO-92, SFN, or 8-pin SO, SOT-23
 Reads over a wide voltage range of 2.8V to
Only Memory (EPROM) communicates with
the economy of one signal plus ground
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
compatibility with other MicroLAN products
for randomly accessing packetized data
write-protected to prevent tampering
additional data can be programmed into
EPROM without disturbing existing data
superseding an old page in favor of a newly
programmed page
programming signals to a single data pin
microprocessor and communicates at up to
16.3 kbits per second
communications requirements to reader
reader first applies voltage
(3-pin), TSOC and flip chip surface mount
package
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
1 of 24
PIN ASSIGNMENT
NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL
CONTACT APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE
INFORMATION, REFER TO APPLICATION NOTE 4132: ATTACHMENT
METHODS FOR THE ELECTRO-MECHANICAL SFN PACKAGE.
BOTTOM VIEW
SFN (APPROX. 6.0mm x 6.0mm x 0.9mm)
1Kb Add-Only Memory
1
09rrd
1
TO-92
DS2502
BOTTOM VIEW
2 3
1
2
2
DATA
GND
DATA
8-PIN SO (150 MIL)
SIDE VIEW
GND
NC
NC
NC
TSOC PACKAGE
Flip Chip, Top View
with Laser Mark,
Contacts Not Visible.
“rrd” = Revision/Date
1 = DATA
2 = GND
1 = DATA; 2, 3 = GND
“rr” = Revision
SOT-23 Package
19-5075; Rev 12/11
TOP VIEW
1
2
3
4
09rr
1
2
3
Top View
SFN PINOUT:
PIN 1: IO
PIN 2: GND
1
DS2502
6
5
4
8
7
6
5
3
NC
NC
NC
2
NC
NC
NC
NC

Related parts for DS2502

DS2502 Summary of contents

Page 1

... Directly connects to a single port pin of a microprocessor and communicates 16.3 kbits per second  8-bit family code specifies DS2502 communications requirements to reader  Presence detector acknowledges when the reader first applies voltage  Low cost TO-92, SFN, or 8-pin SO, SOT-23 ...

Page 2

... The DS2502 consists of a factory-lasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus 1Kb of EPROM which is user-programmable. The power to program and read the DS2502 is derived  ...

Page 3

... LASERED ROM Each DS2502 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3). The 64-bit ROM and ROM Function Control section allow the DS2502 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “ ...

Page 4

HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 64-BIT LASERED ROM Figure 3 8–Bit CRC Code MSB 1-WIRE CRC GENERATOR Figure 4 48–Bit Serial Number LSB MSB 8–Bit Family Code (09h) LSB MSB LSB ...

Page 5

... EPROM The memory map in Figure 5 shows the 1024-bit EPROM section of the DS2502 which is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS2502 that confirms proper receipt of the data ...

Page 6

... To execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the selected data field or until a reset sequence is issued. All bits transferred to the DS2502 and received back by the bus master are sent least significant bit first. ...

Page 7

MEMORY FUNCTION FLOW CHART Figure ...

Page 8

... MEMORY FUNCTION FLOW CHART Figure 6 (cont’d) LEGEND: DECISION MADE BY THE MASTER DECISION MADE BY DS2502 ...

Page 9

MEMORY FUNCTION FLOW CHART Figure 6 (cont’ ...

Page 10

... Read Status command supplies a 8-bit CRC that is based on and always is consistent with the current data stored in the EPROM Status data field. After the 8-bit CRC is read, the bus master will receive logical 1s from the DS2502 until a reset pulse is issued. The Read Status command sequence can be ended at any point by issuing a reset pulse. ...

Page 11

... EPROM data field. After the 8-bit CRC of the last page is read, the bus master will receive logical 1s from the DS2502 until a reset pulse is issued. The Read Data/Generate 8-Bit CRC command sequence can be exited at any point by issuing a reset pulse ...

Page 12

... The bus master will issue the next byte of data using eight write time slots. As the DS2502 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address; the result is an 8-bit CRC of the new data byte and the LSB of the new address ...

Page 13

... DS2502 will not be able to determine if the 8-bit CRC calculated by the bus master agrees with the 8-bit CRC calculated by the DS2502 incorrect CRC is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the DS2502. Also note that the DS2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected EPROM byte ...

Page 14

... This command allows the bus master to read the DS2502’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can be used only if there is a single DS2502 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...

Page 15

... DS2502 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure ...

Page 16

ROM FUNCTIONS FLOW CHART Figure ...

Page 17

... DS2502. During write time slots, the delay circuit determines when the DS2502 will sample the data line. For a read data time slot “0” transmitted, the delay circuit determines how long the DS2502 will hold the data line low overriding the “1” generated by the master. ...

Page 18

... CRC GENERATION The DS2502 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2502 to determine if the ROM data has been received error-free by the bus master. The equivalent ...

Page 19

... DS2502 DS2502 SAMPLING WINDOW 60 µs ≤ t < 120 µs SLOT 1 µs ≤ t < 15 µs LOW1 1 µs ≤ t < ∞ REC DS2502 SAMPLING WINDOW 60 µs ≤ t < t < 120 µs LOW0 SLOT 1 µs ≤ t < ∞ REC 60 µs ≤ t < 120 µs SLOT 1 µ ...

Page 20

PROGRAM PULSE TIMING DIAGRAM Figure ...

Page 21

... Flip Chip SFN This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS ...

Page 22

... Capacitance on the data pin could be 800 pF when power is first applied kΩ resistor is used to pullup the data line normal communications. 10. Maximum 1-Wire voltage for programming parameters is 11.5V to 12.0V; temperature range is -40°C to +50°C. 11. Under certain low-voltage conditions V guarantee a presence pulse. ...

Page 23

... PACKAGE INFORMATION For the latest package outline information and land patterns (footprints www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. ...

Page 24

... Added Package Information section; extended Revision History. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...

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