DS12885 Maxim, DS12885 Datasheet
DS12885
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DS12885 Summary of contents
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... If a primary power failure is detected, the device CC automatically switches to a backup supply. A lithium coin-cell battery can be connected to the V pin on the DS12885 to maintain time and date operation when primary power is absent. The device is accessed through a multiplexed byte-wide interface, which sup- ports both Intel and Motorola modes. ...
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... PDIP, SO, PLCC, TQFP ..................................-55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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DC ELECTRICAL CHARACTERISTICS ( 3.0V over the operating range, unless otherwise noted.) (Note 2) CC BAT A PARAMETER SYMBOL V Current (OSC On); BAT T = +25° 3.0V A BACKUP V Current ...
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Real-Time Clocks AS t ASD AD0–AD7 WRITE AD0–AD7 READ AS t ASD DS t ASD R ASL AD0–AD7 WRITE 4 _____________________________________________________________________ Motorola Bus Read/Write Timing PW ASH t ASED t CYC ...
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AS t ASD DS t ASD R/W CS AD0–AD7 IRQ Release Delay Timing DS RESET IRQ t IRDS PF(MAX) V PF(MIN) RECOGNIZED INPUTS VALID OUTPUTS t CYC PW ASH t ASED ...
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... DR CONDITIONS 3.0V 50pF + 1TTL Gate Input/Output: V 5ns ; MOT, AS, AD0–AD7 = MIN TYP MAX 20 200 300 0 MIN TYP MAX 10 MIN TYP MAX 5 7 TEST CONDITIONS maximum and V minimum IL IH open. BACKUP UNITS ms µs µs UNITS years UNITS pF pF ...
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... MOT RESET AD0–AD7 RLCR Typical Operating Characteristics 32768.70 32768.60 +25°C 32768.50 32768.40 32768.30 32768.20 32768.10 32768.00 3.8 4.0 DIVIDE DIVIDE 16:1 MUX DS12885 CLOCK/CALENDAR UPDATE LOGIC _____________________________________________________________________ Real-Time Clocks OSCILLATOR FREQUENCY vs 4.5 4.8 5.0 5.5 5.3 V (V) CC Functional Diagram DIVIDE BY 64 SQUARE- SQW WAVE ...
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Real-Time Clocks PIN SO, EDIP PLCC TQFP PDIP — — 5–10, 4–11 4– 15, 20 12, 17 ...
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PIN SO, NAME EDIP PLCC TQFP PDIP 11, 15, 20, 22 16, 20, 13, 18, 23, 25 RESET Connection. This ...
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... The IRQ pin is an open-drain output and requires an external pullup resistor to V Connection for a Primary Battery. (DS12885 Only.) Battery voltage must be held between the minimum and maximum limits for proper operation backup supply is not supplied, V must be grounded ...
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... Detailed Description The DS12885 family of RTCs provide 14 bytes of real- time clock/calendar, alarm, and control/status registers and 114 bytes (113 bytes for DS12C887 and DS12C887A) of nonvolatile, battery-backed static RAM. A time-of-day alarm, three maskable interrupts with a common interrupt output, and a programmable square- wave output are available ...
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... Power-Down/Power-Up Considerations The real-time clock continues to operate, and the RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the V input level remain within the minimum and maximum limits when V is not applied. When V is applied and exceeds (power-fail trip point), the device becomes accessi- ...
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... Read/Write Bit. * DS12C887, DS12C887A only. General-purpose RAM on DS12885, DS12887, and DS12887A. Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds regis- ter, 0 bits in the time and date registers can be written to 1, but may be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits ...
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... Read/Write Bit. * DS12C887, DS12C887A only. General-purpose RAM on DS12885, DS12887, and DS12887A. Note: Unless otherwise specified, the state of the registers is not defined when power is first applied. Except for the seconds regis- ter, 0 bits in the time and date registers can be written to 1, but may be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits ...
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Control Registers The real-time clocks have four control registers that are accessible at all times, even during the update cycle. MSB BIT 7 BIT 6 BIT 5 UIP DV2 Bit 7: Update-In-Progress (UIP). This bit is a status flag that ...
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Real-Time Clocks MSB BIT 7 BIT 6 BIT 5 SET PIE Bit 7: SET. When the SET bit is 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to 1, ...
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MSB BIT 7 BIT 6 BIT 5 IRQF PF Bit 7: Interrupt Request Flag (IRQF). This bit is set to 1 when any of the following are true PIE = AIE = ...
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Real-Time Clocks Century Register (DS12C887/DS12C887A Only) The century register at location 32h is a BCD register designed to automatically load the BCD value 20 as the year register changes from 99 to 00. The MSB of this register is not ...
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Table 3. Periodic Interrupt Rate and Square-Wave Output Frequency SELECT BITS t PERIODIC PI REGISTER A INTERRUPT RATE RS3 RS2 RS1 RS0 None 3.90625ms 7.8125ms ...
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... SQW 22 N.C. 21 RCLR 20 V BAT 19 IRQ 18 RESET GND 15 R N.C. SQW N.C. 1 DS12885Q 2 MOT PLCC Pin Configurations MOT N. SQW N. N.C. N.C. AD0 4 21 (RCLR) AD1 5 20 N.C. DS12887 AD2 6 19 IRQ DS12887A ...
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... PDIP 17 GND 24 EDIP 28 PLCC TQFP PROCESS: CMOS SUBSTRATE CONNECTED TO GROUND ____________________________________________________________________ Real-Time Clocks Ordering Information TOP MARK* DS12885 DS12885 DS12885Q DS12885Q DS12885Q DS12885Q DS12885S DS12885S DS12885S DS12885 DS12885 DS12887 DS12887A DS12C887 DS12C887AA Thermal Information THETA-JA (°C/W) THETA-JC (°C/ 105 22 ...
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... Ordering Information table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...