DS12R885 Maxim, DS12R885 Datasheet
DS12R885
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DS12R885 Summary of contents
Page 1
... Rev 6; 4/10 RTCs with Constant-Voltage Trickle Charger General Description The DS12R885 is a functional drop-in replacement for the DS12885 real-time clock (RTC). The device pro- vides an RTC/calendar, one time-of-day alarm, three maskable interrupts with a common interrupt output, a programmable square wave, and 114 bytes of battery- backed static RAM ...
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... BACKUP V (Note (Note 2) IL -33 I CC1 - CCS - (Note (Note 6) MOT I (Note (Note -33 TRIP -5 R1 DS12R885 Only V DS12R885 Only OUT MIN TYP MAX UNITS 2.97 3.3 3.63 V 4.5 5.0 5.5 2 OUT 2.2 V 0.3 -0.3 +0 0.8 2 0.250 0.5 mA 0.140 0.3 -1.0 +1.0 μA -1.0 +1.0 μ ...
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... RTCs with Constant-Voltage Trickle Charger DC ELECTRICAL CHARACTERISTICS (DS12R885 Only 0V 3.2V -40°C to +85°C, unless otherwise noted.) (Note 1) CC BACKUP A PARAMETER SYMBOL V Current (OSC On); BACKUP I BACKUP2 T = +25° 3.0V A BACKUP V Current (Oscillator Off) I BACKUP BACKUPDR AC ELECTRICAL CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C.) (Note 1) ...
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RTCs with Constant-Voltage Trickle Charger AC ELECTRICAL CHARACTERISTICS (V = 2.97V to 3.63V -40°C to +85°C.) (Note PARAMETER SYMBOL Cycle Time Pulse Width, DS Low or R/W High Pulse Width, DS High or R/W Low ...
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RTCs with Constant-Voltage Trickle Charger ASD AD0–AD7 WRITE AD0–AD7 READ AS PW ASH t ASD DS t ASD R ASL AD0–AD7 WRITE _____________________________________________________________________ Motorola Bus Read/Write Timing ASH t ...
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RTCs with Constant-Voltage Trickle Charger AS t ASD DS t ASD R/W CS AD0–AD7 IRQ Release Delay Timing DS RESET IRQ t IRDS PF(MAX) V PF(MIN) RECOGNIZED INPUTS OUTPUTS 6 _____________________________________________________________________ t CYC PW ASH t ASED ...
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... Gate 25pF + 1TTL Gate Input/Output: V 5ns ; MOT, AS, AD0–AD7 = _____________________________________________________________________ MIN TYP MAX 20 200 300 0 MIN TYP MAX 5 MIN TYP MAX 10 10 TEST CONDITIONS maximum and V minimum IL IH open. BACKUP UNITS ms µs µs UNITS Years UNITS ...
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... TEMPERATURE (°C) 8 _____________________________________________________________________ Typical Operating Characteristics vs. V BACKUP 2.5 2.8 3.0 (V) 32768.10 32768.08 32768.06 32768.04 32768.02 32768.00 32767.98 32767.96 32767.94 32767.92 32767. vs. V vs. I BACKUP CC BACKUP (DS12R885) DS12R885 toc02 3.0 0μA -15μA 2.8 -30μA 2.6 -45μA 2.4 -60μA 2.2 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V (V) CC OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY (V) ...
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... DS12R885 by the falling edge of AS. Write data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel timing read cycle, the DS12R885 outputs data during the latter portion of DS (DS and R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is terminated and the bus returns to a high-impedance state as DS transitions low in the case of Motorola timing transitions high in the case of Intel timing ...
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... Ground Chip-Select Input. The active-low chip-select signal must be asserted low for a bus cycle in the DS12R885 to be accessed. CS must be kept in the active state during DS and AS for Motorola timing and during DS and R/W for Intel timing. Bus cycles that take place without asserting CS latch addresses, but no access occurs. When V the DS12R885 inhibits access by internally disabling the CS input ...
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... typical application, RESET can be connected to V DS12R885 and out of power fail without affecting any of the control registers. Interrupt Request Output. The IRQ pin is an active-low output of the DS12R885 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set ...
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... Intel and Motorola modes. The DS12CR887 EDIP integrates a DS12R885 die with a crystal and battery. The charging circuit on the DS12R885 die is disabled. The battery has sufficient capacity to power the oscillator and registers for five years in the absence +25°C. ...
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... RTCs with Constant-Voltage Trickle Charger An external 32.768kHz oscillator can also drive the DS12R885. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is left unconnected. Clock Accuracy The accuracy of the clock is dependent upon the accu- racy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed ...
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RTCs with Constant-Voltage Trickle Charger methods of avoiding any possible incorrect time and calendar reads are covered later in this text. The three alarm bytes can be used in two ways. First, when the alarm time is written in the ...
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RTCs with Constant-Voltage Trickle Charger Table 2B. Time, Calendar, and Alarm Data Modes—Binary Mode ( ADDRESS BIT 7 BIT 6 BIT 5 00H 0 0 01H 0 0 02H 0 0 03H 0 0 AM/PM 04H 0 0 ...
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... RTCs with Constant-Voltage Trickle Charger Control Registers The DS12R885 has four control registers that are accessible at all times, even during the update cycle. BIT 7 BIT 6 BIT 5 UIP DV2 Bit 7: Update-In-Progress (UIP). This bit is a status flag that can be monitored. When the UIP bit the update transfer occurs soon. When UIP the update transfer does not occur for at least 244µ ...
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... The AF bit does not initiate the IRQ signal when the AIE bit is set to 0. The internal functions of the DS12R885 do not affect the AIE bit, but is cleared RESET. Bit 4: Update-Ended Interrupt Enable (UIE). This bit is a read/write bit that enables the update-end flag (UF) bit in Register C to assert IRQ ...
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RTCs with Constant-Voltage Trickle Charger BIT 7 BIT 6 BIT 5 IRQF PF Bit 7: Interrupt Request Flag (IRQF). This bit is set to 1 when any of the following are true PIE = AIE ...
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... RTCs with Constant-Voltage Trickle Charger Nonvolatile RAM (NV RAM) The 114 general-purpose NV RAM bytes are not dedi- cated to any special function within the DS12R885. They can be used by the processor program as battery-backed memory and are fully available during the update cycle. The DS12R885 includes three separate, fully automatic sources of interrupt for a processor ...
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... Update Cycle The DS12R885 executes an update cycle once per second regardless of the SET bit in Register B. When the SET bit in Register B is set to 1, the user copy of the double-buffered time, calendar, and alarm bytes is frozen and does not update as the time increments. ...
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... Maximum time above 150°C is less than 180 seconds. 3. Maximum time above 170°C is less than 100 seconds. 4. Maximum time above 200°C is less than 60 seconds. TOP VIEW MOT AD0 4 AD1 5 DS12R885 AD2 6 AD3 7 AD4 8 AD5 9 AD6 10 AD7 11 GND 12 SO (0.300" ...
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... For the latest package outline information and land patterns, AD3 GND AD2 go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package AD1 GND AD0 drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status ...
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... Absolute Maximum Ratings; removed the DS12R885 and DS12CR887 leaded parts from the Ordering Information table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied ...