DS1390 Maxim, DS1390 Datasheet
DS1390
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DS1390 Summary of contents
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... V and automatically disables the bus CC interface and switches to the backup supply if a power failure is detected. On the DS1390, a single open-drain output provides a CPU interrupt or a square wave at one of four selectable frequencies. The DS1391 replaces the SQW/INT pin with a RST output/ debounced input ...
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... Input Leakage I/O Leakage RST Pin I/O Leakage I LORST DOUT Logic 1 Output I OHDOUT DOUT Logic 0 Output I OHDOUT Logic 0 Output (DS1390/DS1393/DS1394 I SQW/INT; DS1392 SQW, INT; DS1391/DS1393 RST) V Active Supply Current CC (Note 10) 2 _____________________________________________________________________ Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...........................Refer to the IPC/JEDEC + 0 ...
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Low-Voltage SPI/3-Wire RTCs with RECOMMENDED DC OPERATING CONDITIONS (continued -40°C to +85°C, unless otherwise noted. Typical values are at nominal supply voltage and T CC CC(MIN) CC(MAX) A unless otherwise noted.) (Note ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger SCLK CDH t DC W/R DIN DOUT CPHA = 1 NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 1. Figure 1a. Timing Diagram—SPI Read ...
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Low-Voltage SPI/3-Wire RTCs with CPHA = SCLK t CDH t DC DIN W/R WRITE ADDRESS BYTE DOUT NOTE: SCLK CAN BE EITHER POLARITY SHOWN FOR CPOL = 1. Figure 2a. Timing Diagram—SPI ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger AC ELECTRICAL CHARACTERISTICS—3-WIRE INTERFACE ( -40°C to +85°C.) (Note 1) (Figures CC(MIN) CC(MAX) A PARAMETER SYMBOL SCLK Frequency (Note 13) f Data to SCLK ...
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Low-Voltage SPI/3-Wire RTCs with SCLK CDH t DC I/O A0 WRITE ADDRESS BYTE Figure 3. Timing Diagram—3-Wire Read Transfer SCLK CDH t DC I/O A0 WRITE ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger POWER-UP/POWER-DOWN CHARACTERISTICS (T = -40°C to +85°C) (Figures PARAMETER SYMBOL V Detect to Recognize Inputs CC (V Rising Fall Time PF(MAX) V PF(MIN) V Rise Time; ...
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... CC BACKUP Note 6: Measured typ BACKUP SCLK, DIN DS1390/DS1391/DS1394; SCLK, and CE on DS1392/DS1393. Note 7: DOUT, SQW/INT (DS1390/DS1393/DS1394), SQW, and INT (DS1392). Note 8: Note 9: The RST pin has an internal 50kΩ (typ) pullup resistor to V Note 10: I —SCLK clocking at max frequency = 4MHz for 3V and 3.3V versions; 1MHz for 1.8V version; RST (DS1391/DS1393) CCA inactive ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger (V = +3.3V +25°C, unless otherwise noted vs BBSQ1 = 0 BACKUP BACKUP 600 550 500 450 400 350 300 1.3 1.7 2.1 2.5 2.9 3.3 3.7 ...
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... Low-Voltage SPI/3-Wire RTCs with PIN DS1390/ DS1391 DS1392 DS1393 DS1394 — — — — — — — — 6 — — 9 — — — — — — ...
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... Detailed Description The DS1390–DS1394 RTCs are low-power clocks/calen- dars with alarms. Address and data are transferred seri- ally through a 4-wire SPI interface for the DS1390 and DS1391 and through a 3-wire interface for the DS1392, DS1393, and DS1394. The DS1390/DS1391 operate as a slave device on the SPI serial bus ...
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... PF * The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Maxim Real-Time Clocks for addi- tional specifications. The accuracy of the clock is dependent upon the accu- POWERED BY racy of the crystal and the accuracy of the match ...
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... Low-Voltage SPI/3-Wire RTCs with Trickle Charger Address Map Table 3 shows the address map for the DS1390– DS1393 RTC and RAM registers. The RTC registers are located in address locations 00h to 0Fh in read mode, and 80h to 8Fh in write mode. During a multibyte access, when the address pointer reaches 0Fh, it wraps around to location 00h ...
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... Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. The DS1390–DS1393 can run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger All five devices contain one time-of-day/date alarm. Writing to registers 88h through 8Ch sets the alarm. The alarm can be programmed (by the alarm enable and INTCN bits of the control register) to activate ...
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... BIT 7 BIT 6 BIT 5 EOSC 0 Control bits used in the DS1390 become general-pur- pose, battery-backed, nonvolatile SRAM bits in the DS1391. Control Register (0D/8Dh) (DS1390/DS1393/DS1394 Only) BIT 4 BIT 3 RS2 RS1 Bit 2: Interrupt Control (INTCN). This bit controls the SQW/INT signal. When the INTCN bit is set to logic 0, a square wave is output on the SQW/INT pin ...
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... Low-Voltage SPI/3-Wire RTCs with Trickle Charger BIT 7 BIT 6 BIT 5 EOSC 0 BBSQI The INTCN bit used in the DS1390/DS1393/DS1394 becomes the SQW pin-enable bit in the DS1392. This BIT 7 BIT 6 BIT 5 OSF 0 Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time and may be used to judge the validity of the clock and calendar data ...
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... Low-Voltage SPI/3-Wire RTCs with TRICKLE-CHARGE REGISTER (8Fh WRITE, 0Fh READ) BIT 6 BIT 5 BIT 4 BIT 7 TCS3 TCS2 TCS1 TCS0 SELECT NOTE: ONLY 1010b ENABLES CHARGER V CC Figure 8. DS1390–DS1394 Programmable Trickle Charger Table 6. SPI Pin Function MODE CPHA Disable X Write 0 Read 0 Write 1 Read 1 * CPOL is the clock-polarity bit set in the control register of the host microprocessor ...
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... Data transfers can occur one byte at a time or in multi- ple-byte burst mode. After CS is driven low, an address is written to the DS1390/DS1391/DS1394. After the address, one or more data bytes can be written or read. For a single-byte transfer, one byte is read or writ- ten and then CS is driven high ...
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Low-Voltage SPI/3-Wire RTCs with CS SCLK (MODE 0) SCLK (MODE 1) DIN W DOUT Figure 10. SPI Single-Byte Write CS SCLK (MODE 0) SCLK (MODE 1) DIN W HIGH IMPEDANCE DOUT Figure 11. SPI ...
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Low-Voltage SPI/3-Wire RTCs with Trickle Charger CS SCLK DIN WRITE ADDRESS BYTE DIN ADDRESS BYTE READ DOUT HIGH-IMPEDANCE Figure 12. SPI Multiple-Byte Burst Transfer CE SCLK I Figure 13. 3-Wire Single-Byte Read CE SCLK I/O A1 ...
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... Serial-Data Bus The DS1392/DS1393 provide a 3-wire serial-data bus, and support both single-byte and multiple-byte data transfers for maximum flexibility. The I/O pin is the seri- al-data input/output pin. The CE input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data movement between the master (microcontroller) and the slave (DS1392/DS1393) devices ...
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... Low-Voltage SPI/3-Wire RTCs with Trickle Charger TOP VIEW DS1390 BACKUP DS1394 GND μSOP DS1392 V 3 BACKUP GND μSOP 24 ____________________________________________________________________ SQW/INT SCLK BACKUP 7 4 DOUT DIN GND ...
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... Low-Voltage SPI/3-Wire RTCs with CRYSTAL SCLK CPU DS1390/ DOUT DS1394 DIN GND CRYSTAL SCLK CPU DS1392 I/O GND For the latest package outline information and land patterns www.maxim-ic.com/packages. PACKAGE TYPE 10 µSOP SQW/INT ...
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... Added DS1390U-33/V+ to the Ordering Information table. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...