73S1215F Maxim, 73S1215F Datasheet
73S1215F
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73S1215F Summary of contents
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... Rev. 1.4 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More Teridian Semiconductor Corporation offers with its 73S1215F a very comprehensive set of software libraries, including the smart card and USB protocol layers that are pre-approved against USB, Microsoft WHQL and EMV, as well as a CCID reference design. Refer to the 73S12xxF Software User’ ...
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FEATURES 80515 Core: • 1 clock cycle per instruction (most instructions) • CPU clocked up to 24MHz • 64kB Flash memory with security • 2kB XRAM (User Data Memory) • 256 byte IRAM • Hardware watchdog timer Oscillators: • Single ...
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... QFN Package Outline ................................................................................................... 132 7 Ordering Information ...................................................................................................................... 133 8 Related Documentation .................................................................................................................. 133 9 Contact Information ........................................................................................................................ 133 Revision History ...................................................................................................................................... 134 Rev. 1.4 Table of Contents 73S1215F Data Sheet ...
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... Figure 40: Smart Card I/O Circuit.............................................................................................................. 127 Figure 41: PRES Input Circuit ................................................................................................................... 127 Figure 42: PRES Input Circuit ................................................................................................................... 128 Figure 43: USB Circuit .............................................................................................................................. 128 Figure 44: 73S1215F 68 QFN Pinout ....................................................................................................... 129 Figure 45: 73S1215F 44 QFN Pinout ....................................................................................................... 130 Figure 46: 73S1215F 68 QFN Package Drawing ..................................................................................... 131 Figure 47: 73S1215F 44 QFN Package Drawing ..................................................................................... 132 4 Rev. 1.4 ...
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... DS_1215F_003 Tables Table 1: 73S1215F Pinout Description ......................................................................................................... 8 Table 2: MPU Data Memory Map ................................................................................................................ 11 Table 3: Flash Special Function Registers ................................................................................................. 13 Table 4: Internal Data Memory Map ........................................................................................................... 14 Table 5: Program Security Registers .......................................................................................................... 17 Table 6: IRAM Special Function Registers Locations ................................................................................. 18 Table 7: IRAM Special Function Registers Reset Values ........................................................................... 19 Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20 Table 9: PSW Register Flags ...
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Table 83: The 24-bit RTC Trim (sign magnitude value) .............................................................................. 54 Table 84: The INT5Ctl Register .................................................................................................................. 54 Table 86: The ACOMP Register ................................................................................................................. 55 Table 88: The INT6Ctl Register .................................................................................................................. 56 Table 90: The LEDCtl Register ................................................................................................................... 57 Table ...
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... FLASH CORE IRAM INTERFACE 256B ALU WATCH- PMU DOG DATA TIMER XRAM PORTS 2KB ISR SERIAL PERIPHERAL INTERFACE and SFR LOGIC 73S1215F Data Sheet VCC VCC CONTROL LOGIC GND RST CLK SMART CARD I/O ISO INTERFACE AUX1 AUX2 PRES PRESB EXTERNAL SCLK ...
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... SCL SDA Table 1: 73S1215F Pinout Description Description I Figure 27 MPU/USB clock crystal oscillator input pin. A 12MHz crystal is required for USB operation. A 1MΩ resistor is required between pins X12IN and X12OUT. Figure 27 MPU/USB clock crystal oscillator output pin. I Figure 28 RTC clock crystal oscillator input pin ...
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... Smart Card LDO regulator power supply source. A 10μF and a 0.1μF capacitor are required at the VPC input. The 10μF capacitor should be a ceramic type with low ESR. Trace bus signals for ICE. ICE control. ICE control. ICE control. ICE control. 73S1215F Data Sheet 9 ...
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Pin Name ANA_IN SEC 67 2 TEST VDD N GND 9 7 GND RESET See the figures in the ...
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... DS_1215F_003 1.2 Hardware Overview The Teridian 73S1215F single smart card controller integrates all primary functional blocks required to implement a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0-7816 compliant smart card interface, expansion smart card interface, full speed USB 2 ...
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... Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL = 1. Table 3 shows the location and description of the 73S1215F flash-specific SFRs. Any flash modifications must set the CPUCLK to operate at 3.6923 MHz before any flash memory operations are executed to insure the proper timing when modifying the flash memory ...
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... Enables security provisions that prevent external reading of flash memory and CE program RAM. This bit is reset on chip reset and may only be set. Attempts to write zero are ignored. Rev. 1.4 Description PGADDR @ SFR 0xB7. FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled. 73S1215F Data Sheet 13 ...
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Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory address is always one byte wide and can be accessed by either direct or indirect addressing. The Special Function Registers ...
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... XRAM 0x1F 0x18 0x17 0x10 0x0F 0x08 0x07 0x00 Figure 2: Memory Map 73S1215F Data Sheet Use Indirect Direct Access Access Byte RAM SFRs Byte RAM Bit/Byte RAM Register bank 3 Register bank 2 Register bank 1 Register bank 0 Internal Data Memory ...
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Program Security Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE ...
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... The user can force this pin high during boot sequence time to indicate to firmware that sec mode 1 is desired. R/W Bit 1 (SECSET1): See the Program Security section. R/W Bit 0 (SECSET0): See the Program Security section. Rev. 1.4 Table 5: Program Security Registers Description 73S1215F Data Sheet 17 ...
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... SP Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1215F are shown in bold print (gray background). Any read access to unimplemented addresses will return undefined data, while most write access will have no effect. However, a few locations are reserved and not user configurable in the 73S1215F ...
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... Interrupt Priority Register 0 Serial Port 0, Reload Register, low byte Flash Control Flash Page Address Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte Interrupt Request Control Register Timer 2 Control 73S1215F Data Sheet 19 ...
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PSW 0xD0 0x00 KCOL 0XD1 0x1F KROW 0XD2 0x3F KSCAN 0XD3 0x00 KSTAT 0XD4 0x00 KSIZE 0XD5 0x00 KORDERL 0XD6 0x00 KORDERH 0XD7 0x00 BRCON 0xD8 0x00 A 0xE0 0x00 B 0xF0 0x00 1.5.3 External Data Special Function Registers (SFRs) ...
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... B Register: The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register to hold temporary data. Rev. 1.4 Description TRIM Pulse Control FUSE Control VDDFault Control Security Register Miscellaneous Control Register 0 Miscellaneous Control Register 1 LED Control Register 73S1215F Data Sheet 21 ...
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Program Status Word (PSW): MSB CV AC Bit Symbol PSW.7 CV Carry flag. PSW.6 AC Auxiliary Carry flag for BCD operations. PSW.5 F0 General purpose Flag 0 available for user. PSW.4 RS1 Register bank select control bits. The contents of ...
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... Oscillator and Clock Generation The 73S1215F has two oscillator circuits; one for the main CPU clock and another for the RTC. The main oscillator circuit is designed to operate with various crystals or external clock frequencies. An internal divider working in conjunction with a PLL and VCO needs to provide a 96MHz internal clock within the 73S1215F ...
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MCount(2:0) X12IN HIGH XTAL 12.00MHz OSC X12OUT X32IN LOW 32768Hz XTAL OSC X32OUT 32KOSCenb CPUCKDiv See SC Clock descriptions for more accurate diagram SCCKenb Figure 3: Clock Generation and Control Circuits 24 HOSCen HCLK M DIVIDER 12.00MHz /(2 ...
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... MPU Clock Control register (MPUCKCtl). Rev. 1.4 = 96MHz register must be bound between a value The possible F (MHz) Mcount (N) XTAL 12.00 2 9.60 3 8.00 4 6.86 5 6.00 6 0x0A Table 13: The MCLKCtl Register SCEN USBEN 32KEN MCT.2 Function . The default value is MCount = 2h such that XTAL 73S1215F Data Sheet LSB MCT.1 MCT.0 25 ...
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... The CPU clock is available as an output on pin CPUCLK (68-pin version only). 1MΩ 12MHz 22pF Note: The crystals should be placed as close as possible to the IC, and vias should be avoided. 26 0x0C Table 14: The MPUCKCtl Register MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0 Function 73S1215F 22pF 22pF Figure 4: Oscillator Circuit LSB 32KHz 22pF Rev. 1.4 ...
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... DS_1215F_003 1.7.2 Power Control Modes The 73S1215F contains circuitry to disable portions of the device and place it into a lower power standby mode. This is accomplished by either shutting off the power or disabling the clock going to the block. The miscellaneous control registers MISCtl0, control over the power modes. There is also a device power down mode that will stop the core, clock subsystem and the peripherals connected to it ...
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USR0 USR1 USR[7:0] Control USR2 USR3 USR4 USRxINTSrc set to 4(ext INT0 high) USR5 or USR6 6(ext INT0 low) USR7 INT4 INT5 RESETB Notes: 1. The counters are clocked by the MPUCLK Terminal count (high at overflow) ...
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... Serial port pins select. Rev. 1.4 0x00 Table 15: The INT5Ctl Register USBINT Function 0x00 Table 16: The MISCtl0 Register – – – – Function PCON register to stop the CPU core. The RTC will stay active 73S1215F Data Sheet LSB KPIEN KPINT LSB SLPBK SSEL 29 ...
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Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 MSB – – Bit Symbol MISCtl1.7 – MISCtl1.6 – Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is passed through with no change. When FRPEN = 0 a one-shot ...
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... MCLK = (2*2 + 4)*12.00MHz = 96MHz. *Note: The HSOEN bit should never be set under normal circumstances. Power down control should only be initiated via use of the PWRDN bit in MISCtl0. Rev. 1.4 0x0A Table 18: The MCLKCtl Register SCEN USBEN 32KEN MCT.2 Function 73S1215F Data Sheet LSB MCT.1 MCT.0 31 ...
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Power Control Register 0 (PCON): 0x87 The SMOD bit used for the baud rate generator is setup via this register. MSB SMOD – Bit Symbol PCON.7 SMOD If SM0D = 1, the baud rate is doubled. PCON.6 – PCON.5 – ...
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... External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators, the 73S1215F, for example the USB interface, USR I/O, RTC, smart card interface, analog comparators, etc ...
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Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt service is terminated by a ...
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... Bit Symbol IEN2.0 ES1 ES1 = 0 – disable serial channel interrupt. Rev. 1.4 0x00 Table 21: The IEN1 Register EX6 EX5 EX4 EX3 Function 0x00 Table 22: The IEN2 Register – – – – Function 73S1215F Data Sheet LSB EX2 – LSB – ES1 35 ...
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Timer/Counter Control Register (TCON): 0x88 MSB TF1 TR1 Bit Symbol TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control. TCON.3 IE1 Interrupt 1 ...
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... Table 25: The IRCON Register EX6 IEX5 IEX4 IEX3 Function Table 26: External MPU Interrupts Connection Polarity see USRIntCtlx see USRIntCtlx Edge selectable Edge selectable _Fault, Analog Comp DD 73S1215F Data Sheet LSB IEX2 – Flag Reset Automatic Automatic Automatic Automatic N/A Automatic N/A Automatic N/A Automatic 37 ...
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... Enable external interrupt 5 EX6 Enable external interrupt 6 1.7.3.4 Power Down Interrupt Logic The 73S1215F contains special interrupt logic to allow INT0 to wake up the CPU from a power down (CPU STOP) state. See the Power Control Modes 1.7.3.5 Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 28. ...
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... Chip Reset External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 73S1215F Data Sheet LSB IP1.1 IP1.0 Interrupt Vector Address 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 ...
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... UART The 80515 core of the 73S1215F includes two separate UARTs that can be programmed to communicate with a host. The 73S1215F can only connect one UART at a time since there is only one set of TX and Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each UART has a different set of operating modes that the user can select according to their needs ...
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... Sets CPU to Stop mode. Sets CPU to Idle mode. 0x00 Table 37: The BRCON Register – – – – Function If BSEL = 0, the baud rate is derived using timer 1. If BSEL = 1 the baud rate generator circuit is used. . 73S1215F Data Sheet LSB STOP IDLE LSB – – 41 ...
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... Table 38: The MISCtl0 Register – – – Function This bit places the 73S1215F into a power down state UART loop back testing mode. The pins TXD and RXD are to be connected together externally (with SLPBK =1) and therefore: SLPBK SSEL Mode 0 0 ...
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... These two bits set the UART0 mode: Mode Description SM0 0 N 8-bit UART 0 2 9-bit UART 1 3 9-bit UART 1 th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, 73S1215F Data Sheet LSB TI0 RI0 SM1 S1CON is outputted as the 9th 43 ...
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Serial Interface Control Register (S1CON): 0x9B The function of the serial port depends on the setting of the Serial Port Control Register S1CON. MSB SM – Bit Symbol S1CON.7 SM S1CON.6 – S1CON.5 SM21 S1CON.4 REN1 S1CON.3 TB81 S1CON.2 RB81 ...
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... TH0 and the Timer 1 load registers are designated 0x00 start their associated timers when set. Table 41: The TMOD Register M1 M0 GATE C/T Timer 0 Function TCON register), a counter is incremented every falling edge description. description. 73S1215F Data Sheet User (USR) (TMOD LSB ...
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Table 42: Timers/Counters Mode Description M1 M0 Mode 0 0 Mode Mode Mode Mode 3 Mode 0 Putting either timer/counter into mode 0 configures 8-bit timer/counter with a ...
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... WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of the WDTREL register and WDT is automatically reset. Rev. 1.4 0x00 Table 43: The TCON Register TF0 TR0 IE1 IT1 Function 73S1215F Data Sheet LSB IE0 IT0 47 ...
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Interrupt Enable 0 Register (IEN0): 0xA8 MSB EAL WDT Bit Symbol IEN0.7 EAL EAL = 0 – disable all interrupts. IEN0.6 WDT Watchdog timer refresh flag. Set to initiate a refresh of the watchdog timer. Must be set directly before ...
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... Seven bit reload value for the high-byte of the watchdog timer. This to WDREL6-0 value is loaded to the WDT when a refresh is triggered by a WDTREL.0 consecutive setting of bits WDT and SWDT. Rev. 1.4 0x00 Table 46: The IP0 Register IP0.5 IP0.4 IP0.3 IP0.2 Function 0x00 Table 47: The WDTREL Register Function 73S1215F Data Sheet LSB IP0.1 IP0.0 LSB 49 ...
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... User (USR) Ports The 73S1215F includes 9 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the USR and UDIR SFRs. Each pin declared as USR can be configured independently as an input or output with the bits of the UDIRn registers ...
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... Table 52: The USRIntCtl2 Register U3IS.5 U3IS.4 – U2IS.2 0x00 Table 53: The USRIntCtl3 Register U5IS.5 U5IS.4 – U4IS.2 0x00 Table 54: The USRIntCtl4 Register U7IS.5 U7IS.4 – U6IS.2 73S1215F Data Sheet LSB U0IS.1 U0IS.0 LSB U2IS.1 U2IS.0 LSB U4IS.1 U4IS.0 LSB U6IS.1 U6IS.0 51 ...
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Real-Time Clock with Hardware Watchdog (RTC) Figure 9 shows the block diagram of the Real Time Clock. The RTC block uses the 32768Hz oscillator signal and divider logic to produce 0.5-second time marks. The time marks are used to ...
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... In addition to the basic software watchdog timer included in the 80515 MPU, an independent, robust, fixed-duration, hardware watchdog timer (WDT) is included with the 73S1215F RTC. The Watch Dog timer will give the MPU ½ second to respond to the RTC Interrupt. If the processor does not perform an RTC Interrupt service, a full RESET will be performed. The RTC interrupt is connected to the core interrupt “ ...
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There are 3 sets of registers to load the RTC 24-bit accumulator, 32-bit counter and 23-bit trim registers. The registers are loaded when the RTCLD bit is set in RTCCtl. Register RTCCnt3 RTCCnt[31:24] Register Table 58: The 24-bit RTC Trim ...
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... DS_1215F_003 1.7.9 Analog Voltage Comparator The 73S1215F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The comparator control register should not be modified when the analog interrupt (ANAIEN bit in the INT6Ctl generated when modifying the threshold ...
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External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. 2 INT6Ctl.3 I2CIEN I C interrupt enabled. 2 INT6Ctl.2 I2CINT I C interrupt ...
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... DS_1215F_003 1.7.10 LED Drivers The 73S1215F F provides four dedicated output pins for driving LEDs. The LED driver pins can be configured as current sources that will pull to ground to drive LEDs that are connected to VDD without the need for external current limiting resistors. These pins may be used as general purpose outputs with the programmed pull-down current and a strong (CMOS) pull-up, if enabled ...
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... I C Master Interface The 73S1215F includes a dedicated fast mode, 400kHz I or write bytes of data per data transfer frame. The MPU communicates with the interface through six dedicated SFR registers: • Device Address (DAR) • Write Data (WDR) • Secondary Write Data (SWDR) • ...
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... LSB MSB LSB 1 10-17 ACK bit ACK bit 2 Figure 10 Write Mode Operation IEN1 and IRCON registers for masking and flag operation. 73S1215F Data Sheet 18 STOP condition Secondary Write Data [7:0] MSB LSB 18 19-26 27 ACK bit STOP condition 2 C Master Bus. 2 ...
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Figure 11 shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA MSB SCL START START condition condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA MSB SCL START condition 60 2 ...
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... WDR.7 WDR.6 WDR.5 WDR.4 Data to be written to the I WDR.3 WDR.2 WDR.1 WDR.0 Rev. 1.4 0x00 Table 63: The DAR Register DVADR.1 Function 0x00 Table 64: The WDR Register WDR.4 WDR.3 WDR.2 Function 2 C slave device. 73S1215F Data Sheet LSB DVADR.0 I2CRW LSB WDR.1 WDR.0 61 ...
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I2C Secondary Write Data Register (SWDR): 0XFF82 MSB SWDR.7 SWDR.6 SWDR.5 Bit SWDR.7 SWDR.6 SWDR.5 SWDR.4 Second Data byte to be written to the I and Status register (CSR) is set = 1. SWDR.3 SWDR.2 SWDR.1 SWDR.0 I2C Read Data ...
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... Table 67: The SRDR Register SRDR.4 SRDR.3 SRDR.2 Function 2 C slave device if bit 0 (I2CLEN) of the Control 0x00 Table 68: The CSR Register – – – AKERR Function 2 C transaction. Automatically reset to 0 when the bus 73S1215F Data Sheet LSB SRDR.1 SRDR.0 LSB I2CST I2CLEN 63 ...
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External Interrupt Control Register (INT6Ctl): 0xFF95 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I When set =1, the I ...
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... DS_1215F_003 1.7.12 Keypad Interface Keypad Interface The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) The 73S1215F supports a 30-button (6 row x 5 column) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. interface using 11 dedicated I/O pins. Figure 12 shows a simplified block diagram of the keypad interface. ...
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The selection of the clock source is made external to this block, by setting bit 3 – 32KBEN – in the Disabling the 32kHz oscillator will source the 1kHz clock from the 12MHz main ...
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... Is (are) the key(s) Yes released ? (*) No KSCAN Register: Debouncing Time (*) Key release is cheked by looking for a low level on any row. 73S1215F Data Sheet KSTAT Register: Enable HW Scanning Enable Keypad Interrupt KSCAN Register: Debouncing Time KSIZE Register: Keypad Size Definition KSCAN Register: Scanning Rate ...
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Keypad Column Register (KCOL): 0xD1 This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning. MSB – – ...
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... KEYDET cannot cause an interrupt. KEYDET can still get set even if the interrupt is not enabled. Rev. 1.4 0x00 Table 72: The KSCAN Register Function 0x00 Table 73: The KSTAT Register – – KEYCLK HWSCEN KEYDET KYDTEN Function 73S1215F Data Sheet LSB LSB 69 ...
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... ROWSIZ.2 Bit Symbol KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ.2 Defines the number of rows in the keypad. Maximum number is 6 given KSIZE.4 ROWSIZ.1 the number of row pins on the package. Allows for a reduced keypad size for scanning. KSIZE.3 ROWSIZ.0 KSIZE.2 COLSIZ.2 Defines the number of columns in the keypad. Maximum number is 5 KSIZE ...
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... This bit indicates the Keypad logic has set Key_Detect bit and a key INT5Ctl.0 KPINT location may be read. Cleared on read of register. Rev. 1.4 Table 76: The KORDERH Register 5COL.0 4COL.2 4COL.1 Function (msb). 0x00 Table 77: The INT5Ctl Register Function 73S1215F Data Sheet 0x00 LSB 4COL.0 3COL.2 LSB KPIEN KPINT 71 ...
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... USB Interface 1.7.14 USB Interface The 73S1215F provides a single interface, full speed -12Mbps - USB device port as per the Universal The 73S1215F provides a single interface, full speed -12Mbps - USB device port as per the Universal Serial Bus Specification, Revision 2.0 (backward compatible with USB 1.1). USB circuitry gathers the Serial Bus Specification, Revision 2 ...
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... Data Memory space. The FIFOs are dedicated for USB storage and are unused in a configuration that is not using USB. All registers in the USB interface are located in external data memory address (XRAM) space starting at address FC00’h. Rev. 1.4 73S1215F Data Sheet 73 ...
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... USBPEN MISCtl1.0 USBCON Note: When using the USB on the 73S1215F, external 24Ω series resistors must be added to the D+ and D- signals to provide the proper impedance matching on these pins. The USB peripheral block is not able to support read or write operations to the USB SFR registers when the MPU clock is running at MPU clock rates of 12MHz or greater ...
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... CKCON.0 CKWT.0 110 = 6 wait states. 111 = 7 wait states. Rev. 1.4 0x01 – – – CKWT.2 CKWT.1 CKWT.0 Function Use when MPU clock is <12MHz. Use when MPU clock is between 12 and 16MHz. Use when MPU clock is 24MHz. 73S1215F Data Sheet LSB 75 ...
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... Smart Card Interface Function The 73S1215F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple smart cards to be connected using the Teridian 8010 family of interface devices. Figure 15 shows the simplified block diagram of the card circuitry (UART + family of interface devices ...
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... If support for the auxiliary lines is necessary for the externa n eed to be handled manually through the USR GPIO pins. The external 8010 devices directly connect the I/O (SIO) and clock (SCLK) signals and control is handled via the I Figure 16 shows how multiple 8010 devices can be connected to the 73S1215F. VPC PRES PRES ...
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... ISO 7816 UART An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1215F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection of the desired interface is made by register SCSel. Control of the ...
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... Time allowed for ATR timeout, set by the Note: If the RSTCRD bit is set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be de-asserted after t4. Figure 17: Asynchronous Activation Sequence Timing Rev. 1 STSTO register. 73S1215F Data Sheet t4 See Note ATR starts t5 RLength register. 79 ...
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Firmware sets VCCSEL delay or Card Event IO RST CLK CMDVCCnB VCC t1: Time after either a “card event” occurs or firmware sets the VCCSela and VCCSelb bits to 0 (see t5, VCCOff_tmr) occurs until RST is ...
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... There are two, two-byte FIFOs that are used to buffer transmit and receive data. During a T=0 processing parity error is detected by the 73S1215F during message reception, an error signal (BREAK) will be generated to the smart card. The byte received will be discarded and the firmware notified of the error. ...
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... CRC/LRC calculation (if required). 1.7.15.5 Synchronous Operation Mode The 73S1215F supports synchronous operation. When sync mode is selected for either interface, the CLK signal is generated by the ETU counter. The values in FDReg, SCCLK, and the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must be selected to obtain a smart card clock signal ...
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... I2CMODE SCIE b7, was “WTOIEN”, becomes RLenIEN. Rev. 1 (STXCtl, b7), the IO or SIO signal is directly controlled by SCCtl and SCECtl register. The state of the data in the SCInt b7, was “WAITTO”, becomes RLenINT interrupt, and 73S1215F Data Sheet SPrtcol b6 “MODE9/8B”, 83 ...
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... Note that in Sync mode input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK, either from the card or from the 73S1215F. The RST signal to the card is directly controlled by the RSTCRD bit (non-inverted) via the MPU and is shown as an example of a possible RST pattern. ...
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... RLength RLen=0 5 Count MAX I2CMode = 1:ACK Bit (to/from card) I2CMode = 0: Data from TX fifo RLength Count MAX generate the Stop bit in Synchronous Mode. 73S1215F Data Sheet START Bit Data from TX FIFO Rlen=1 7 STOP Bit Min ½ ETU ...
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CLK Data from Card IO (Bit 8) RLength Count Rlen=8 RLength = 9 RLength Interrupt RX data Protection Bit Data (Bit 9) TX/RX Mode Bit TX = '1' 1._ Interrupt generated when Rlength counter is Max CLK RLength Count Rlen=8 ...
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... Select Smart Card Interface – These bits select the interface that is using the IS0 UART. These bits do not activate the interface. Activation is performed by the VccCtl 1 = Enabled Disabled. When enabled, ISO UART is bypassed and the I/O line is controlled via the registers. 73S1215F Data Sheet LSB SELSC.0 BYPASS – register. SCCtl and ...
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Smart Card Interrupt Register (SCInt): 0xFE01 When the smart card interrupt is asserted, the firmware can read this register to determine the actual cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be ...
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... RXDAEN Rx Data Available Interrupt Enable. SCIE.3 TXEVEN TX Event Interrupt Enable. SCIE.2 TXSNTEN TX Sent Interrupt Enable. SCIE.1 TXEREN TX Error Interrupt Enable. SCIE.0 RXEREN RX Error Interrupt Enable. Rev. 1.4 0x00 Table 83: The SCIE Register RXDAEN TXEVEN TXSNTEN TXEREN Function 73S1215F Data Sheet LSB RXEREN 89 ...
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... If not set, the deactivation sequence shall start when the VCCTMR times out. VccCtl.3 VCCOK (Read only). Indicates that V VccCtl.2 – VccCtl.1 – This bit controls the power down mode of the 73S1215F circuit. VccCtl.0 SCPWRDN 1 = power down normal operation. 90 0x00 Table 84: The VccCtl Register RDYST VCCOK Function VCCSEL ...
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... If not, the VCCSEL bits will be cleared. The time value is a count of the 32768Hz clock and is given by tto = VCCTMR(3:0) * 30.5μs. A value of 0000 results in no timeout, not zero time, and activation requires that RDYST is set and RDY goes high. 73S1215F Data Sheet LSB 91 ...
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Card Status/Control Register (CRDCtl): 0xFE05 This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This register be written to properly configure Debounce, Detect_Polarity (= 1), and the pull-up/down enable before ...
Page 93
... Cleared when read. This bit generates TXERR interrupt. Rev. 1.4 0x00 Table 86: The STXCtl Register TXEMTY TXUNDR LASTTX Function SCCtl (or SCECtl) register rather than the TX Protocol Mode Register 73S1215F Data Sheet LSB TX/RXB BREAKD for more detail. 93 ...
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STX Data Register (STXData): 0xFE07 MSB STXDAT.7 STXDAT.6 STXDAT.5 Bit STXData.7 STXData.6 STXData.5 Data to be transmitted to smart card. Gets stored in the TX FIFO and then extracted by the hardware and sent to the selected smart card. When ...
Page 95
... SRXData.7 SRXData.6 SRXData.5 SRXData.4 (Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is read by the firmware. SRXData.3 SRXData.2 SRXData.1 SRXData.0 Rev. 1.4 0x00 Table 89: The SRXData Register Function 73S1215F Data Sheet LSB 95 ...
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Smart Card Control Register (SCCtl): 0xFE0A This register is used to monitor reception of data from the smart card. MSB RSTCRD – Bit Symbol 1 = Asserts the RST (set RST = 0) to the smart card interface ...
Page 97
... SCLK SCLK enabled SCLK disabled. When disabled, SCLK level is SCECtl.0 SCLKOFF determined by SCLKLVL. This bit has no effect if in bypass mode. Rev. 1.4 0x00 Table 91: The SCECtl Register SIOD – – Function 73S1215F Data Sheet 2 C clock LSB SCLKLVL SCLKOFF 97 ...
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C4/C8 Data Direction Register (SCDIR): 0xFE0C This register determines the direction of the internal interface C4/C8 lines. After reset, all signals are tri-stated. MSB – – Bit Symbol SCDIR.7 – SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D 1 = ...
Page 99
... ATR. Rev. 1.4 0x03 Table 93: The SPrtcol Register 0 TMODE CRCEN Function SCCtl register bits for direct firmware control. SCECtl register bits for direct firmware control. 73S1215F Data Sheet LSB CRCMS RCVATR SRXCtl 99 ...
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SC Clock Configuration Register (SCCLK): 0xFE0F This register controls the internal smart card (CLK) clock generation. MSB – – ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0 Bit Symbol SCCLK.7 – SCCLK.6 – SCCLK.5 ICLKFS.5 Internal Smart Card CLK Frequency Select – ...
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... Force Parity Error – enabled disabled. Used for test purposes. If SParCtl.0 FORCPE enabled, the UART will generate a parity error on a character received from the smart card. Rev. 1.4 0x00 Table 96: The SParCtl Register Function 73S1215F Data Sheet LSB INSPE FORCPE 101 ...
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Byte Control Register (SByteCtl): 0xFE12 This register controls the processing of characters and the detection of the TS byte. When receiving, a Break is asserted at 10.5 ETU after the beginning of the start bit. Break from the card is ...
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... Data Sheet LSB DVAL.1 DVAL.0 0101 0110 0111 1488 1860 1860⊕ 20⊕ 1101 1110 1111 2048 2048⊕ 2048⊕ 20 20⊕ ...
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Table 101: Divider Values for the ETU Clock Fi code 0000 Di 372 F→ code D↓ 0001 1 744 0010 2 372 0011 4 186 0100 8 93 1000 12 62 0101 16 47 1001 20 37 0110 32 23 ...
Page 105
... CRCEN is not set and in mode T1). They are available to the firmware to use if desired. Rev. 1.4 0xFF, (CRCLsB): 0xFE15 Table 103: The CRCMsB Register CRC.13 CRC.12 CRC.11 Table 104: The CRCLsB Register CRC.5 CRC.4 CRC.3 73S1215F Data Sheet 0xFF LSB CRC.10 CRC.9 CRC.8 LSB CRC.2 CRC.1 CRC.0 105 ...
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Block Guard Time Register (BGT): 0xFE16 This register contains the Extra Guard Time Value (EGT) most-significant bit. The Extra Guard Time indicates the minimum time between the leading edges of the start bit of consecutive characters. The delay is depends ...
Page 107
... These registers (BWTB0, BWTB1, BWTB2, BWTB3) are used to set the Block Waiting Time(27:0) (BWT). All of these parameters define the maximum time the 73S1215F will have to wait for a character from the smart card. These registers serve a dual purpose. When T=1, these registers are used to set up the block wait time ...
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ATR Timeout Registers (ATRLsB): 0xFE20 MSB ATRTO.7 ATRTO.6 ATRTO.5 MSB ATRTO.15 ATRTO.14 ATRTO.13 These registers (ATRLsB and ATRLsB) form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading edge of the first character and leading edge of ...
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... SCESYN 0 DISPAR BRKGEN BRKDET DETTS DIRTS BRKDUR (1:0) FVAL(3:0) CRC(15:8) CRC(7:0) EGT(7:0) BWT(23:16) BWT(15:8) BWT(7:0) CWT(15:8) CWT(7:0) ATRTO(15:8) ATRTO(7:0) TSTO(7:0) RLen(7:0) 73S1215F Data Sheet SelSC(1:0) BYPASS TXEVNT TXSENT TXERR TXEVEN TXSNTEN TXERR VCCOK VCCTMR(3:0) DETPOL PUENB PDEN TXUNDR LASTTX TX/RXB RXFULL ...
Page 110
... Note: The V Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The DD 73S1215F has the capability to burn fuses at the factory to set the factory default to any of these voltages. Contact Teridian for further details. 110 falls below the V DD 0x00 Table 118: The VDDFCtl Register – ...
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... USR8 TEST USR2 33 USR2 TBUS0 3 34 ROW3 INT2 3 3. 0.1uF 0.1uF 0.1uF Figure 26: 73S1215F Typical Application Schematic 73S1215F Data Sheet OPTIONAL LCD DISPLAY SYSTEM 16 CHARACTER BY 2 LINES U5 5.0V RV1 C29 C30 10K + 2 1uF 0.1uF LCD BRIGHTNESS ADJUST LED3 LED1 LED2 LED0 3 ...
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... Electrical Specification 3.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to V Parameter DC Supply voltage Supply Voltage V PC Storage Temperature Pin Voltage (except card interface) ...
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Digital IO Characteristics These requirements pertain to digital I/O pin types with consideration of the specific pin function and configuration. The LED(3:0) pins have pull-ups that may be enabled. The Row pins have 100KΩ pull- ups. Symbol Parameter Voh ...
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Oscillator Interface Requirements Symbol Parameter Low-Power Oscillator Requirements. No External Load Beside The Crystal And Capacitor Is Permitted On Xout32. Pxtal Power In Crystal IIL Input Leakage Current High-Frequency Oscillator (Xin) Parameters. XIN Is Used As Input For External ...
Page 115
USB Interface Requirements Parameter Receiver Parameters Differential input sensitivity Differential common mode range Single ended receiver threshold Transmitter Levels Low Level Output Voltage High Level Output Voltage Output Resistance (1) Driver output resistance PD Pullup Resistor (to VDD) Transceiver ...
Page 116
Parameter C = 50pf, series 24Ω, 1% source termination resistor included L Rise Time USBTR Fall Time USBTF Rise/fall time matching TRFM Output signal crossover VCRS voltage Source Jitter to Next TDJ1 Transition Source Jitter For Paired TDJ2 Transitions Receiver ...
Page 117
Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General conditions, -40°C < T < 85°C, 4.75V < V Card supply Voltage V including ripple and CC noise V V Ripple CCrip CC Card supply ...
Page 118
... Output rise time, fall times Input rise, fall times Internal pull-up resistor PU FD Maximum data rate MAX Reset and Clock for Card Interface, RST, CLK V Output level, high OH V Output level, low OL Output voltage when V INACT outside of session ...
Page 119
DC Characteristics Symbol Parameter I Supply Current DD I Supply Current PC V supply current when PC I PCOFF 3.8 Voltage / Temperature Fault Detection Circuits Symbol Parameter V fault Voltage supervisor ...
Page 120
Equivalent Circuits X12LIN ESD ENABLE ENABLEb X32LIN ESD 120 VDD Figure 27: 12 MHz Oscillator Circuit VDD >1MEG Figure 28: 32kHz Oscillator Circuit X12OUT ESD To circuit X32OUT ESD To circuit Rev. 1.4 ...
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Output Disable Data From circuit To circuit Output Disable Data From circuit Rev. 1.4 VDD STRONG PFET STRONG NFET Figure 29: Digital I/O Circuit VDD STRONG PFET STRONG NFET Figure 30: Digital Output Circuit PIN ESD PIN ESD 121 ...
Page 122
Pull-up Disable Output Disable Data From circuit To circuit Figure 31: Digital I/O with Pull Up Circuit Output Disable Data From circuit To circuit Pull-down Enable Figure 32: Digital I/O with Pull-Down Circuit 122 VDD VERY WEAK PFET STRONG PFET ...
Page 123
To circuit Pull-up Disable Output Disable Data From circuit To circuit Rev. 1.4 ESD Figure 33: Digital Input Circuit STRONG PFET STRONG NFET Figure 34: Keypad Row Circuit PIN VDD 100k OHM PIN ESD 123 ...
Page 124
Output Disable Data From circuit To circuit 124 VDD 1200 OHMS MEDIUM PFET STRONG NFET Figure 35: Keypad Column Circuit PIN ESD Rev. 1.4 ...
Page 125
Pullup Disable Data From circuit To circuit Current Value Control PIN Figure 37: Test and Security Pin Circuit Rev. 1.4 VDD STRONG PFET STRONG NFET Figure 36: LED Circuit This buffer has a special input threshold: Vih>0.7*VDD ...
Page 126
From circuit 126 To Comparator Input PIN ESD Figure 38: Analog Input Circuit VCC Figure 39: Smart Card Output Circuit STRONG ESD PFET PIN ESD STRONG NFET Rev. 1.4 ...
Page 127
From circuit To circuit To circuit Pull-down Enable Rev. 1.4 STRONG PFET 125ns DELAY STRONG NFET Figure 40: Smart Card I/O Circuit VERY WEAK NFET Figure 41: PRES Input Circuit VCC RL=11K ESD IO PIN ESD VDD ESD PIN ESD ...
Page 128
Pull-up Enable To circuit RP_ENb DP_OUT DP_IN RCV_IN DM_IN DM_OUT OUTPUT ENABLEb 128 VERY WEAK PFET Figure 42: PRES Input Circuit VDD VDD 1500 Ω ZOUT= 20Ω ESD OUTPUT ENABLEb IN_P IN_N VDD ZOUT= 20Ω ESD Figure 43: USB Circuit ...
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... ROW2 24 GND VDD 28 USR5 29 USR4 30 USR3 31 USR8 32 USR2 33 ROW3 34 Rev. 1.4 CAUTION: Use handling procedures necessary for a static sensitive component. TERIDIAN 73S1215F Figure 44: 73S1215F 68 QFN Pinout ISBR 68 SEC 67 RESET 66 VDD 65 PRES AUX1 62 AUX2 61 VCC 60 RST 59 GND 58 CLK 57 PRESB 56 VPC ...
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... QFN Pinout TXD 12 USR7 13 USR6 14 GND VDD 18 USR5 19 USR4 20 USR3 21 USR2 22 130 CAUTION: Use handling procedures necessary for a static sensitive component. TERIDIAN 73S1215F Figure 45: 73S1215F 44 QFN Pinout VDD 44 PRES AUX1 41 AUX2 40 VCC 39 RST 38 GND 37 CLK 36 PRESB 35 VPC 34 Rev. 1.4 ...
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... QFN Package Outline Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 8.00 7. TOP VIEW 8.00 0.42 0.24/0.60 6.30 6.15/6.45 0.45 0.42 0.24/0.60 6.30 6.15/6.45 6.40 BOTTOM VIEW Figure 46: 73S1215F 68 QFN Package Drawing Rev. 1.4 7.75 8.00 12° PIN#1 ID R0. 0.20 2 0.15/0.25 3 6.40 8.00 0.40 FOR ODD TERMINAL/SIDE 0.65 0.85 0.2 0.00/0.05 SEATING ...
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... QFN Package Outline Notes: 5.1mm x 5.1mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 7.00 6. TOP VIEW 7.00 0.42 0.24/0.60 5.10 4.95/5.25 0.45 0.42 0.24/0.60 5.10 4.95/5.25 5.00 BOTTOM VIEW Figure 47: 73S1215F 44 QFN Package Drawing 132 6.75 7.00 12° PIN#1 ID R0. 0.23 2 0.18/0.30 3 5.00 7.00 0.50 FOR ODD TERMINAL/SIDE 0.65 0.85 0.2 0.00/0.05 SEATING ...
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... Evaluation Board User’s Guide 73S12xxF Software User’s Guide 73S12xxF Synchronous Card Design Application Note 9 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S1215F, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 ...
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Revision History Revision Date Description 1.1 2/2/2007 First publication. 1.3 11/6/2007 On protocols T=0, T=1” to “ISO-7816 UART for protocols T=0, T=1” and 32-cycle references. In preferred location for the user’s preboot code, may not be page-erased ...
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In PRES, SEC and TEST pins. In “FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes the page address for page erase. The page size is 512 (200h) bytes and there are 128 pages within the flash memory. The ...
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Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Windows is a registered trademark of Microsoft Corporation. Signum Systems is a trademark of Signum Systems Corporation. ExpressCard is a registered ...