DS8007A Maxim, DS8007A Datasheet
DS8007A
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DS8007A Summary of contents
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... Ordering Information PART TEMP RANGE SUPPORTED DS8007A-EAG+ -40°C to +125° auxiliary 48 LQFP + Denotes a lead(Pb)-free/RoHS-compliant device. EMV is a trademark owned by EMVCo LLC. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. ...
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... All Other Pins...........................................-0. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Alarm Pulse Width External Clock Frequency Internal Oscillator Voltage on V Pin UP ...
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Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Output Low Card Voltage Inactive Mode Output Current Output Low Voltage V CCx ...
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Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued +3.3V +3.3V +25°C, unless otherwise noted.) (Note 1) DD DDA A PARAMETER SYMBOL Output Low V Voltage Card Inactive Output Current I Mode Internal Pullup R ...
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... Note 2: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maxi- mum rise and fall time is 10ns. Note 3: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs. 6 _______________________________________________________________________________________ ...
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Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR MULTIPLEXED PARALLEL BUS (V = 3.3V 3.3V +25°C, unless otherwise noted.) (Figure 1) DD DDA A PARAMETER SYMBOL XTAL1 Cycle Time t CY(XTAL1) ALE Pulse Width ...
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Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR NONMULTIPLEXED PARALLEL BUS (READ AND WRITE 3.3V 3.3V +25°C, unless otherwise noted.) (See Figure 2.) DD DDA A PARAMETER RD High to CS Low ...
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Multiprotocol Dual Smart Card Interface AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR CONSECUTIVE READ/WRITE TO URR/UTR/TOC (V = 3.3V 3.3V +25°C, unless otherwise noted.) DD DDA A PARAMETER SYMBOL SEE FIGURE 3 RD Pulse Width t W(RD) RD ...
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Multiprotocol Dual Smart Card Interface I/Ox TBE BIT INT WR/CS t W(WR) t CRED BIT WR(UTR) Figure 4. Timing Between Two Write Operations in Register UTR t WR/CS W(WR) t CRED BIT WR(TOC) Figure 5. Timing Between Two Write Operations ...
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Multiprotocol Dual Smart Card Interface PIN NAME Reset Output. This active-high output is provided for resetting external devices. The RSTOUT pin is driven high until the DELAY pin reaches V 1 RSTOUT so it can externally be pulled down. The ...
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... CS and WR are low. Active-Low Parallel Bus Write Strobe Input. In multiplexed mode, this input indicates when the host WR 37 processor is writing information to the DS8007A. In nonmultiplexed mode, a low on this pin signals the bus is engaged in a read or write operation Active-Low Chip-Select Input ...
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... UP Figure 6. Block Diagram ______________________________________________________________________________________ no edge (activity) is detected on the ALE pin. Once a rising edge is detected on the ALE pin, the DS8007A is placed into the multiplexed mode of operation. Once in the multiplexed mode of operation, a reset/power cycle or the deassertion of CS forces the device to the non- multiplexed mode. Connecting the ALE pin to V ground forces the device into nonmultiplexed parallel bus mode ...
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... RD and WR strobe input signals are used to enable a read or write operation, respectively, if the DS8007A is selected (i.e 0). See the AC tim- ing for the multiplexed parallel bus mode found earlier in this data sheet. 14 ...
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... Control Registers Special control registers that the host computer/micro- controller accesses through the parallel bus manage most DS8007A features. Many of the registers, although only mentioned once in the listing, are dupli- cated for each card interface. The PDR, GTR, UCR1, UCR2, and CCR registers exist separately for each of the three card interfaces ...
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... Bits Identification Bits (CSR7 to CSR4). These bits provide a method for software to identify the device as follows: 0011 = DS8007A revision Ax Bit 3: Reset ISO UART (RIU). When this bit is cleared (0), most of the ISO UART registers are reset to their initial values. This bit must be cleared for at least 10ns prior to initiating an activation sequence ...
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Multiprotocol Dual Smart Card Interface 7 6 Address 02h PD7 PD6 RW-0 RW unrestricted read unrestricted write value after reset; all bits unaffected by RIU = 0. Bits Programmable ETU Divider ...
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... Insertion of card A or card B (detected by PRLA or PRLB). • Withdrawal of card A or card B (detected by PRLA or PRLB). • Reassertion of the CS pin to select the DS8007A (CS must be deasserted after setting PDWN = 1 for this event to exit from power-down). • INTAUXL bit is set due to change in INTAUX (INTAUXL bit must be cleared first). • ...
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Multiprotocol Dual Smart Card Interface 7 6 Address 06h FTE0 FIP R-0 RW unrestricted read unrestricted write value after reset. This register is reset to 0uuu00uub on RIU = 0. Bit 7: FIFO Threshold ...
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Multiprotocol Dual Smart Card Interface 7 6 Address 07h — — R-0 R unrestricted read unrestricted write value after reset. This register is reset to 0011uuuub on RIU = 0. Note: The AUX card ...
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Multiprotocol Dual Smart Card Interface 7 6 Address 09h TOL7 TOL6 W-0 W unrestricted read unrestricted write value after reset. This register is unchanged on RIU = 0. Bits Timeout Counter ...
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... Bit 4: Control Ready (CRED). This bit signals the host device that the DS8007A is ready to handle the next write operation to UTR or TOC or the next read opera- tion of URR. When CRED = 0, the DS8007A is still work- ing on the previous operation and cannot correctly process the new read/write request. When CRED = 1, the DS8007A is ready for the next read/write request. This “ ...
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... PE bit is set indicate that the par- ity error limit has been reached. In transmit mode, the DS8007A attempts to retransmit a character up to (PEC2–PEC0) times (when NAK’d by the card) before the PE bit is set. Retransmission attempts are automati- cally made at 15 ETU from the previous start bit. If PEC2– ...
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Multiprotocol Dual Smart Card Interface 7 6 Address 0Eh TO3 TO2 R-0 R unrestricted read unrestricted write value after reset. All register bits are reset to 00000000b on RIU = 0. Note: If any ...
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Multiprotocol Dual Smart Card Interface 7 6 Address 0Fh — PRTLB R-0 R unrestricted read unrestricted write value after reset always reflects state of external device pin. This register is reset to ...
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... The DELAY pin is an external indicator of the state of internal power and can also be driven external hold the device in a reset state. An external capac- itor is usually attached to this pin, defining the time constant of a power-on delay for the DS8007A. When V is below the voltage threshold V DD ...
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Multiprotocol Dual Smart Card Interface V = 2.1V TO 2.5V RST ~1.25V DRST DELAY RSTOUT INT SUPL BIT Figure 8. Voltage Supervisor ______________________________________________________________________________________ RESULTING FROM V < RST DELAY DRIVEN LOW EXTERNALLY t W ...
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Multiprotocol Dual Smart Card Interface Activation Sequencing An activation sequence can only be requested by a host device through the parallel bus interface. The host can request an activation sequence for a specific card (card A or card B) by ...
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Multiprotocol Dual Smart Card Interface Deactivation Sequencing The host device can request a deactivation sequence by resetting the START bit to 0 for the desired card interface. The deactivation (from the deassertion of the START bit, step 1 of the ...
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Multiprotocol Dual Smart Card Interface Timeout Counter Operation The timeout counter assists the host device in timing real-time events associated with the communication pro- tocols: the Work Wait Time (WWT), Block Waiting Time (BWT), etc. The timeout counter registers count ...
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Multiprotocol Dual Smart Card Interface Table 3. Timeout Counter Configurations (continued) TOC VALUE TOR3 TOR2 71h Start Bit 75h Start Bit 7Ch Start Bit 85h Stopped E5h Software Start Bit/Autostop (RCV); F1h Start Bit (XMT) Start Bit/Autostop F5h (RCV); Start ...
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Multiprotocol Dual Smart Card Interface ISO UART Implementation The CSR.RIU control bit resets the ISO UART. The CSR.RIU must be reset prior to any activation. CSR.RIU must be returned software before any UART action can take place. ...
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... RSTx START BIT Figure 11. ETU Generation Standard Clock Frequencies The DS8007A supports I/O communication and CLKx frequency generation compliant to the following stan- dards: ISO 7816, EMV2000, and GSM11-11. Each of these standards has an allowable CLKx frequency range and a defined relationship between CLKx fre- quency and ETU (baud rate) generation that is support- ed initially and after negotiation ...
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Multiprotocol Dual Smart Card Interface parameters continue to be used until a successful PPS exchange is completed. The negotiated Fn, Dn values are then used after a successful PPS exchange. If the card comes up in specific mode (i.e., TA(2) ...
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... protocol. The AUTOC bit should not be modified during a card session. Framing Error Detection The DS8007A monitors the selected card I/Ox signal at 10.25 ETU following each detected start bit. If the I/Ox signal is not in the high state at this point in time, the USR ...
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... UTR register. Some smart cards require extra time to handle informa- tion received from an interface device. To allow this extra time, the DS8007A implements a Guard Time Register (GTR) per card interface. This register is pro- grammed with the number of extra ETU that should be ...
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... ISO UART tests for correct parity on each received character. If UCR1.FIP is configured to 1, inverse parity is expected. This control can be useful in testing that the ICC prop- erly detects error signals generated by the DS8007A and retransmits requested characters. LAST CHARACTER TO TRANSMIT LCT BIT WRITTEN SOFTWARE, THEN LOAD UTR ...
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... Configuring PEC2–PEC0 bits to 001b means one repetition in reception is allowed and that the DS8007A generates an error signal only once per character receive attempt. When the consecutive pari- ty error counter reaches 000b and a character is CHARACTER N ETU TIME => ...
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... FIFO. When UCR1.FIP = 1 during reception, only those char- acters with incorrect parity are stored to the receive FIFO since the DS8007A is checking for inverse parity. For the protocol, the receive character is stored to the FIFO no matter whether the parity checks cor- rectly or not ...
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Multiprotocol Dual Smart Card Interface 40 ______________________________________________________________________________________ Typical Operating Circuit ...
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... EMVCo approval shall be provided by the party providing such products or services, and not by EMVCo and EMVCo accepts no liability whatsoever in connection therewith. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. ...