LMH0031VS/NOPB

Manufacturer Part NumberLMH0031VS/NOPB
DescriptionIC DESER/DESCRAM DGTL VID 64TQFP
ManufacturerNational Semiconductor
TypeDescrambler/Deserializer
LMH0031VS/NOPB datasheet
 

Specifications of LMH0031VS/NOPB

ApplicationsSDTV/HDTVMounting TypeSurface Mount
Package / Case64-TQFP, 64-VQFPInput Voltage3.3 V
Supply Voltage (max)3.45 VSupply Voltage (min)3.15 V
Maximum Operating Temperature+ 70 CMinimum Operating Temperature0 C
Mounting StyleSMD/SMTFor Use WithSD131EVK - BOARD EVALUATION LMH0031
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther names*LMH0031VS
*LMH0031VS/NOPB
LMH0031VS
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LMH0031
SMPTE 292M/259M Digital Video Deserializer /
Descrambler with Video and Ancillary Data FIFOs
General Description
The LMH0031 SMPTE 292M / 259M Digital Video
Deserializer/Descrambler with Video and Ancillary Data
FIFOs is a monolithic integrated circuit that deserializes and
decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial
component video data, to 20-bit parallel data with a synchro-
nized parallel word-rate clock. It also deserializes and de-
codes
SMPTE
259M,
270Mbps,
SMPTE 344M (proposed) 540Mbps serial component video
data, to 10-bit parallel data. Functions performed by the
LMH0031 include: clock/data recovery from the serial data,
serial-to-parallel data conversion, SMPTE standard data de-
coding, NRZI-to-NRZ conversion, parallel data clock genera-
tion, word framing, CRC and EDH data checking and han-
dling, Ancillary Data extraction and automatic video format
determination. The parallel video output features a variable-
depth FIFO which can be adjusted to delay the output data
up to 4 parallel data clock periods. Ancillary Data may be
selectively extracted from the parallel data through the use
of masking and control bits in the configuration and control
registers and stored in the on-chip FIFO. Reverse LSB dith-
ering is also implemented.
The unique multi-functional I/O port of the LMH0031 pro-
vides external access to functions and data stored in the
configuration and control registers. This feature allows the
designer greater flexibility in tailoring the LMH0031 to the
desired application. The LMH0031 is auto-configured to a
default operating condition at power-on or after a reset com-
mand. Separate power pins for the PLL, deserializer and
other functional circuits improve power supply rejection and
noise performance.
The LMH0031 has a unique Built-In Self-Test (BIST) and
video Test Pattern Generator (TPG). The BIST enables com-
prehensive testing of the device by the user. The BIST uses
the TPG as input data and includes SD and HD component
video test patterns, reference black, PLL and EQ pathologi-
cals and a 75% saturation, 8 vertical colour bar pattern, for
all implemented rasters. The colour bar pattern has optional
transition coding at changes in the chroma and luma bar
data. The TPG data is output via the parallel data port.
The LMH0030, SMPTE 292M / 259M Digital Video Serializer
with Ancillary Data FIFO and Integrated Cable Driver, is the
ideal complement to the LMH0031.
Ordering Information
Order Number
LMH0031VS
© 2006 National Semiconductor Corporation
The LMH0031’s internal circuitry is powered from +2.5 Volts
and the I/O circuitry from a +3.3 Volt supply. Power dissipa-
tion is typically 850mW. The device is packaged in a 64-pin
TQFP.
Features
n SDTV/HDTV serial digital video standard compliant
n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps
360Mbps
and
and 1.485 Gbps serial video data rates with
auto-detection
n LSB de-dithering option
n Uses low-cost 27MHz crystal or clock oscillator
reference
n Fast VCO lock time:
n Built-in self-test (BIST) and video test pattern generator
(TPG)*
n Automatic EDH/CRC word and flag processing
n Ancillary Data FIFO with extensive packet handling
options
n Adjustable, 4-deep parallel output video data FIFO
n Flexible control and configuration I/O port
n LVCMOS compatible control inputs and clock and data
outputs
n LVDS and ECL-compatible, differential, serial inputs
n 3.3V I/O power supply and 2.5V logic power supply
operation
n Low power: typically 850mW
n 64-pin TQFP package
n Commercial temperature range 0˚C to +70˚C
* Patent applications made or pending.
Applications
n SDTV/HDTV serial-to-parallel digital video interfaces for:
— Video editing equipment
— VTRs
— Standards converters
— Digital video routers and switchers
— Digital video processing and editing equipment
— Video test pattern generators and digital video test
equipment
— Video signal generators
Package Type
64-Pin TQFP
DS201796
January 2006
<
500 µs at 1.485 Gbps
NS Package Number
VEC-64A
www.national.com

LMH0031VS/NOPB Summary of contents

  • Page 1

    ... LMH0031. Ordering Information Order Number LMH0031VS © 2006 National Semiconductor Corporation The LMH0031’s internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipa- tion is typically 850mW. The device is packaged in a 64-pin TQFP ...

  • Page 2

    Typical Application www.national.com 2 20179601 ...

  • Page 3

    Block Diagram 3 20179602 www.national.com ...

  • Page 4

    Connection Diagram www.national.com 64-Pin TQFP Order Number LMH0031VS See NS Package Number VEC-64A 4 20179603 ...

  • Page 5

    Absolute Maximum Ratings It is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace speci- fied devices are required, please contact the National Semiconductor Sales Office / Distributors for availability and specifications. CMOS I/O ...

  • Page 6

    Required Input Conditions Symbol Parameter Ancillary / Control Data f ACLK Clock Frequency DC Duty Cycle, Ancillary Clock ACLK Ancillary / Control Clock and Data Rise Time, Fall r f Time Setup Time ...

  • Page 7

    AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3). Symbol Parameter Serial Video Data Inputs BR Serial Input Data Rate SDI Rise Time, Fall Time r f Parallel Video Data Outputs ...

  • Page 8

    AC Electrical Characteristics Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are referenced 0V. SSSI Note 3: Typical values are stated ...

  • Page 9

    Test Circuit 9 20179607 www.national.com ...

  • Page 10

    Timing Diagram Device Operation INTRODUCTION The LMH0031 SMPTE 292M/259M Deserializer/Decoder is used in digital video signal origina- tion and destination equipment: cameras, video tape record- ers, telecines, editors, standards converters, video test and other equipment. It decodes and converts serial ...

  • Page 11

    Device Operation (Continued) FIGURE 1. Optional Input Biasing Scheme The SMPTE descrambler receives NRZI serial data, con- verts it to NRZ, then decodes it to either 10-bit standard definition or 20-bit high definition parallel video data using 9 4 the ...

  • Page 12

    Device Operation (Continued) ANCILLARY/CONTROL DATA PATH The 10-bit ancillary and Control Data Port AD[9:0] serves two functions in the LMH0031. Ancillary Data from the An- cillary Data FIFO is output from this port after its recovery from the video data ...

  • Page 13

    Device Operation (Continued) FIGURE 2. Control Data Read Timing (2 read and 1 write cycle shown) Ancillary Data Functions The LMH0031 can recover Ancillary Data from the serial data stream. This Ancillary Data and related control charac- ters are defined ...

  • Page 14

    Device Operation (Continued) Figure 4 shows the relationship of clock, data and control signals for reading Ancillary Data from the port AD[9:0]. In Ancillary Data read mode, 10-bit Ancillary Data is routed from the Ancillary Data FIFO and read from ...

  • Page 15

    Device Operation (Continued) cally. EDH errors are reported in the EDH0, EDH1, and EDH2 register sets of the configuration and control registers. Updated or new EDH check words and flags may be gener- ated and inserted in the data. EDH ...

  • Page 16

    Device Operation (Continued) TEST PATTERN GENERATOR (TPG) AND BUILT-IN SELF-TEST (BIST) The LMH0031 includes an on-board, parallel video test pat- tern generator (TPG). Four test pattern types are available in both HD and SD formats, NTSC and PAL standards, and ...

  • Page 17

    Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary Register Function Bits EDH and CRC Operations CRC Error (SD/HD) 1 CRC Error Luma 1 CRC Error Chroma 1 CRC Replace 1 Full-Field Flags 5 Active Picture Flags 5 ...

  • Page 18

    Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary (Continued) Register Function Bits LSB Clipping Enable 1 Sync Detect Enable 1 De-Dither Enable 1 Vert. De-Dither Enable 1 Lock Detect 1 Unscrambled 1 Video Data Out TPG and ...

  • Page 19

    Device Operation (Continued) TABLE 2. Control Register Bit Assignments (Continued) Bit 7 Bit 6 ANC 6 (register address 18h) ANC FIFO SHORT MSG ANC PARITY 90% FULL DETECT FORMAT 0 (register address 0Bh) FRAMING SD ONLY HD ONLY MODE FORMAT ...

  • Page 20

    Device Operation (Continued) TABLE 3. Control Register Addresses Register Name EDH 0 EDH 1 EDH 2 ANC 0 ANC 1 ANC 2 ANC 3 ANC 4 ANC 5 ANC 6 FORMAT 0 FORMAT 1 TEST 0 VIDEO INFO 0 I/O ...

  • Page 21

    Device Operation (Continued) reported via the ANC Checksum Error bit. ANC Checksum Error is available as an output on the multifunction I/O port. ANC 1 AND 2 (Addresses 05h and 06h) The extraction of Ancillary Data packets from video data ...

  • Page 22

    Device Operation (Continued) Format Code Format [4,3,2,1,0] 00001 SDTV 174 00010 SDTV, 36 SMPTE 267 00011 SDTV, 27 SMPTE 125 01001 SDTV, 54 ITU-R BT 601.5 01010 SDTV, 36 ITU-R BT 601.5 01011 SDTV, 27 ITU-R BT 601.5 ...

  • Page 23

    Device Operation (Continued) > Test Pattern Select Word Bits Video Raster Standard 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black PLL Path. EQ Path. Colour Bars 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 274M) ...

  • Page 24

    Device Operation (Continued) > Test Pattern Select Word Bits 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black PLL Path. EQ Path. Colour Bars (SD BIST) 625 Line, 25 Frame, 27 MHz, PAL 4x3 (ITU-T BT.601) Ref. ...

  • Page 25

    Device Operation (Continued) VIDEO CONTROL 0 (register address 55h) The EXTERNAL V bit is a special application function CLK which enables use of an external VCXO as a substitute for the internally generated V . Additional circuitry is enabled CLK ...

  • Page 26

    Device Operation (Continued) TABLE 6. Control Register Bit, Pin[n] SEL[5:0] Codes for I/O Port Pin Mapping Register Bit [5] reserved 0 FF Flag Error 0 AP Flag Error 0 ANC Flag Error 0 CRC Error (SD/HD) 0 ANC FIFO 90% ...

  • Page 27

    Pin Descriptions Pin Name 1 AD9 2 AD8 3 AD7 4 AD6 5 AD5 6 V SSD 7 AD4 8 AD3 9 AD2 10 AD1 11 AD0 12 V DDD 13 A CLK 14 IO7 15 IO6 16 IO5 17 ...

  • Page 28

    Pin Descriptions (Continued) Pin Name 50 V CLK 51 V DDPLL 52 V SSPLL 53 R REF SSSI 56 SDI 57 SDI 58 V DDSI 59 V SSIO 60 XTALi/EXT CLK 61 XTALo 62 V ...

  • Page 29

    Application Information output timing practices, especially critical at HD data rates. The power pins feeding the I/O should have low inductance connections to the power and ground planes recom- mended that these connections use at least two vias ...

  • Page 30

    Application Information The control voltage output from R BB the loop filter consisting of a 22.1kΩ resistor in series with a 10nF capacitor, combined in parallel with a 100pF capacitor. This gives a loop bandwidth of 1.5kHz. Since the control ...

  • Page 31

    ... BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...