LMH0031VS/NOPB National Semiconductor, LMH0031VS/NOPB Datasheet - Page 20

no-image

LMH0031VS/NOPB

Manufacturer Part Number
LMH0031VS/NOPB
Description
IC DESER/DESCRAM DGTL VID 64TQFP
Manufacturer
National Semiconductor
Type
Descrambler/Deserializerr
Datasheet

Specifications of LMH0031VS/NOPB

Applications
SDTV/HDTV
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Input Voltage
3.3 V
Supply Voltage (max)
3.45 V
Supply Voltage (min)
3.15 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
For Use With
SD131EVK - BOARD EVALUATION LMH0031
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*LMH0031VS
*LMH0031VS/NOPB
LMH0031VS

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LMH0031VS/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
www.national.com
Device Operation
EDH 0 (register 01h)
The EDH Full-Field flags F/F UES, F/F IDA, F/F IDH, F/F
EDA andF/F EDH are defined in SMPTE RP 165. The flags
are updated automatically when the EDH function is enabled
and data is being received.
The EDH ENABLE bit, when set, enables operation of the
EDH generator function during SD operation. The default
condition of this bit is set (ON).
The EDH FORCE bit, when set, causes updated EDH pack-
ets to be inserted in the parallel output data regardless of the
previous condition of EDH checkwords and flags in the input
serial data. This function may be used in situations where
video content has been edited thus making the previous
EDH information invalid. The default condition of this bit is
reset (OFF).
The CRC ERROR bit indicates that errors in either the EDH
checksums (SD) or CRC checkwords (HD) were detected in
the serial input data. This bit is a combined function which
indicates the presence of either EDH errors during SD op-
eration or CRC errors during HD operation.
EDH 1 (register 02h)
The EDH Active Picture flags A/P UES, A/P IDA, A/P IDH,
A/P EDA andA/P EDH are defined in SMPTE RP 165. The
flags are updated automatically when the EDH function is
enabled and data is being received.
EDH 0
EDH 1
EDH 2
ANC 0
ANC 1
ANC 2
ANC 3
ANC 4
ANC 5
ANC 6
FORMAT 0
FORMAT 1
TEST 0
VIDEO INFO 0
I/O PIN 0 CONFIG
I/O PIN 1 CONFIG
I/O PIN 2 CONFIG
I/O PIN 3 CONFIG
I/O PIN 4 CONFIG
I/O PIN 5 CONFIG
I/O PIN 6 CONFIG
I/O PIN 7 CONFIG
VIDEO CONTROL 0
VIDEO CONTROL 1
REFERENCE CLOCK
TABLE 3. Control Register Addresses
Register Name
(Continued)
Hexadecimal
Address
0B
0C
0D
0E
01
02
03
04
05
06
07
08
17
18
0F
10
12
13
14
15
16
55
56
67
11
20
Specific types of CRC errors in incoming HD serial data are
reported in the CRC ERROR LUMA and CRC ERROR
CHROMA bits.
The CRC REPLACE bit, when set, causes the CRCs in the
incoming data to be replaced with CRCs calculated by the
LMH0031. The bit is normally reset (OFF).
EDH 2 (register 03h)
The EDH Ancillary Data flags ANC UES, ANC IDA, ANC
IDH, ANC EDA andANC EDH are defined in SMPTE RP
165. The flags are updated automatically when the EDH
function is enabled and data is being received.
The status of EDH flag errors in incoming SD serial data are
reported in the ffFlagError, apFlagError and ancFlagError
bits. Each of these bits is the logical-OR of the correspond-
ing EDH and EDA flags.
ANC 0 (Address 04h)
The V FIFO Depth[2:0] bits control the depth of the video
FIFO which preceeds the parallel output data drivers. The
depth can be set from 0 to 4 stages by writing the corre-
sponding binary code into these bits. For example: to set the
Video FIFO depth at two registers, load 11010XXXXXb into
the ANC 0 control register (where X represents the other
functional bits of this register).
Note: When changing some but not all bits in a register and
to retain unchanged other data previously stored in the
register, read the register’s contents and logically-OR this
with the new data. Then write the modified data back into the
register.
Flags for ANC FIFO EMPTY, ANC FIFO 90% FULL, ANC
FIFO FULL and ANC FIFO OVERRUN are available in the
configuration and control register set. These flags can also
be assigned as outputs on the multi-function I/O port. ANC
FIFO EMPTY when set indicates that the FIFO contains no
data. ANC FIFO 90% FULL indicates when the FIFO is at
90% of capacity. Since it is virtually impossible for the host
processor to begin extracting data from the FIFO after it has
been flagged as full without the possibility of an overrun
condition occurring, ANC FIFO 90% FULL is used as an
advanced command to the host to begin extracting data from
the FIFO. To be used properly, ANC FIFO 90% FULL should
be assigned as an output on the multi-function I/O port and
monitored by the host system. Otherwise, inadvertent loss of
ancillary packet data could occur. ANC FIFO FULL when set
indicates that the FIFO registers are completely filled with
data.
The ANC FIFO OVERRUN flag indicates that an attempt to
write data into a full FIFO has occurred. ANC FIFO OVER-
RUN can be reset by reading the bit’s status via the ancillary/
Control port. If an overrun occurrs, the status of the FIFO
message tracking will be invalidated. In this event, the FIFO
should be flushed to reset the message tracking pointers.
Any messages then in the FIFO will be lost.
The ANC Checksum Force bit, under certain conditions,
enables the overwriting of Ancillary Data checksums re-
ceived in the data. Calculation and insertion of new Ancillary
Data checksums is controlled by the ANC Checksum Force
bit. If a checksum error is detected (calculated and received
checksums do not match) and the ANC Checksum Force
bit is set, the ANC Checksum Error bit is set and a new
checksum is inserted in the Ancillary Data replacing the
previous one. If a checksum error is detected and the ANC
Checksum Force bit is not set, the checksum mismatch is

Related parts for LMH0031VS/NOPB