LMH0031VS/NOPB National Semiconductor, LMH0031VS/NOPB Datasheet - Page 22

• Manufacturer Part Number: LMH0031VS/NOPB
• Description: IC DESER/DESCRAM DGTL VID 64TQFP
• Manufacturer: National Semiconductor
• Type: Descrambler/Deserializerr

Specifications of LMH0031VS/NOPB

• Applications: SDTV/HDTV
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Input Voltage: 3.3 V
• Supply Voltage (max): 3.45 V
• Supply Voltage (min): 3.15 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: SD131EVK - BOARD EVALUATION LMH0031
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LMH0031VS; *LMH0031VS/NOPB; LMH0031VS

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Device Operation
[4,3,2,1,0]
The HD Only bit when set to a logic-1 locks the LMH0031
into the high definition data range and frequency. In systems
designed to handle only high definition signals, enabling HD
Only reduces the time required for the LMH0031 to establish
frequency lock and determine the HD format being pro-
cessed.
The SD Only bit when set to a logic-1 locks the LMH0031
into the standard definition data ranges and frequencies. In
systems designed to handle only standard definition signals,
enabling SD Only reduces the time required for the
LMH0031 to establish frequency lock and determine the
format being processed. When SD Only and HD Only are
set to logic-0, the device operates in SD/HD mode.
The Framing Mode bit in the Format 0 register and Fram-
ing Enable in the Video Info 0 register combine with Fram-
ing Enable to control the manner in which the LMH0031
aligns framing. When Framing Mode and Framing Enable
are both reset, the LMH0031 aligns on the first valid TRS
character. If another TRS occurs that is not on a word
boundary, the NSP bit is set until the next TRS that is on a
word boundary occurs. When Framing Mode is set to a
logic-1, the LMH0031 operates similarly to the CLC011 when
NSP is tied to FE. An alternative configuration that operates
identically can be achieved with the LMH0031 by mapping
NSP as an output and Framing Enable as an input on the
Multifunction I/O bus and externally connecting them. In this
case Framing Mode should be reset to a logic-0. When
Framing Mode is reset and Framing Enable is set, the
LMH0031 realigns on every valid TRS. The initial state of
Framing Mode is set following a reset or at power-on.
FORMAT 1 (Address 0Ch)
The LMH0031 automatically determines the format of the
incoming serial data. The result of this operation is stored in
the FORMAT 1 register. The Format[4:0] bits identify which
Format
00001
00010
01001
01010
10001
10010
10100
00011
01011
10011
11001
11010
Code
11100
11101
SDTV, 54
SDTV, 36
SDTV, 27
SDTV, 54
SDTV, 36
SDTV, 27
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
HDTV, 74.25
Format
(Continued)
RP 174
SMPTE 267
SMPTE 125
ITU-R BT 601.5
ITU-R BT 601.5
ITU-R BT 601.5
SMPTE 260
SMPTE 274
SMPTE 274
SMPTE 274
SMPTE 274
SMPTE 295
SMPTE 274
SMPTE 296 (1, 2)
Spec.
TABLE 4. Video Raster Format Parameters
Frame
Rate
30P
25P
24P
60P
60I
60I
60I
50I
50I
50I
30I
30I
25I
25I
22
of the many possible video data standards that the LMH0031
can process is being received. These format codes follow
the same arrangement as for the Format Set[4:0] bits.
These formats and codes are given in Table 4. Bit Format[4]
when set indicates that HD data is being processed. When
reset, SD data is indicated. Format[3] when set indicates
that PAL data is being processed. When reset NTSC data is
being processed. Format[2:0] correspond with one of the
sub-standards given in the table. Note that the LMH0031
does not distinguish or log the data rate differences between
HD data at 74.25Mhz and 74.25MHz/1.001.
The H, V, and F bits correspond to input TRS data bits 6, 7
and 8, respectively. The meaning and function of this data is
the same for both standard definition (SMPTE 125M) and
high definition (SMPTE 292M luminance and colour differ-
ence) video data. Polarity is logic-1 equals HIGH-true. These
bits are registered for the duration of the applicable field.
TEST 0 REGISTER (Address 0Dh)
The Test Pattern Select bits determine which test pattern is
output when the Test Pattern Generator (TPG) mode or the
Built-in Self-Test (BIST) mode is enabled. Table 5 gives the
codes corresponding to the various test patterns. All HD
colour bar test patterns are inherently BIST data. BIST test
patterns for SD are: NTSC, 27MHz, 4x3 Colour Bars and
PAL, 27MHz, 4x3 PLL Pathological.
The TPG Enable bit when set to a logic-1 enables the Test
Pattern Generator function and built-in self-test (BIST).
The Pass/Fail bit indicates the result of the built-in self-test.
This bit is a logic-1 for a pass condition.
Lines
1250
1125
1125
1125
1125
1125
1125
525
525
525
625
625
625
750
Active Lines
507/487*
507/487*
507/487*
1035
1080
1080
1080
1080
1080
1080
577
577
577
720
Samples
3432
2288
1716
3456
2304
1728
2200
2200
2200
2640
2640
2376
2750
1650
Samples
Active
2880
1920
1440
2880
1920
1440
1920
1920
1920
1920
1920
1920
1920
1280