MAX3815CCM+D Maxim Integrated Products, MAX3815CCM+D Datasheet - Page 7

• Manufacturer Part Number: MAX3815CCM+D
• Description: IC EQUALIZER VIDEO 48-TQFP
• Manufacturer: Maxim Integrated Products
• Type: Video Equalizerr

Specifications of MAX3815CCM+D

• Applications: HDMI, DVI, Receivers
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 48
• Termination Type: SMD
• No. Of I/o's: 1
• Supply Voltage Min: 3V
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Data Rate Max: 1.65Gbps
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 1. Functional Diagram
analog nVGA links, must handle a variety of resolutions
and screen update rates. The actual range of digital
serial rates is roughly 250Mbps to 1.65Gbps. For appli-
cations requiring ultra-high resolutions (e.g., QXGA), a
“double-link” TMDS interface is used and is composed
of six data links plus the clock, requiring two MAX3815
ICs with the clock going to both ICs. See Figure 2.
The MAX3815 can be used to extend any TMDS inter-
face as used under the following trademarked names:
DVI (digital visual interface), DFP™ (digital flat-panel),
PanelLink, ADC™ (Apple display connector), and
HDMI (high-definition multimedia interface).
Loss-of-clock signal is indicated by the CLKLOS out-
put. A low level on CLKLOS indicates that the signal
power on the RXC_IN pins has dropped below a
threshold. When there is sufficient input voltage to the
channel (typically greater than 100mV
CLKLOS is high. The CLKLOS output is suitable for
indicating problems with the transmission link caused
by, for example, a broken cable, a defective driver, or a
lost connection to the equalizer.
Loss-of-Clock Signal ( CLKLOS ) Output
TMDS Digital Video Equalizer for DVI/HDMI
RXC_IN+/-
RX2_IN+/-
RX1_IN+/-
RX0_IN+/-
CLKLOS
_______________________________________________________________________________________
TERMINATED
3.3V CML
TERMINATED
3.3V CML
TERMINATED
3.3V CML
TERMINATED
3.3V CML
CLOCK LOS
DETECTOR
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
INPUT
INPUT
INPUT
P-P
differential),
ADAPTIVE
ADAPTIVE
ADAPTIVE
MAX3815
EQ
EQ
EQ
Figure 2. Connection Scheme for MAX3815 in Dual Link
Application
ADC is a trademark of Apple Computer, Inc.
DFP is a trademark of Video Electronics Standards Association
(VESA).
CLK
D0
D1
D2
D3
D4
D5
AMPLIFIER
AMPLIFIER
AMPLIFIER
AMPLIFIER
LIMITING
LIMITING
LIMITING
LIMITING
MAX3815
DRIVER
DRIVER
DRIVER
DRIVER
RX2_OUT+/-
RX1_OUT+/-
RX0_OUT+/-
EQCONTROL
RXC_OUT+/-
OUTON
OUTLEVEL
MAX3815
Cables
D0
D1
D2
CLK
D3
D4
D5
7