MM74C906M Fairchild Semiconductor, MM74C906M Datasheet

IC BUFFER HEX OP/DR N-INV 14SOIC

MM74C906M

Manufacturer Part Number
MM74C906M
Description
IC BUFFER HEX OP/DR N-INV 14SOIC
Manufacturer
Fairchild Semiconductor
Series
74Cr
Datasheets

Specifications of MM74C906M

Logic Type
Buffer/Line Driver, Non-Inverting with Open Drain
Number Of Elements
6
Number Of Bits Per Element
1
Voltage - Supply
3 V ~ 15 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Family
74C
Number Of Channels Per Chip
Hex
Polarity
Non-Inverting
Supply Voltage (max)
15 V
Supply Voltage (min)
3 V
Maximum Operating Temperature
85 C
Mounting Style
SMD/SMT
Maximum Power Dissipation
500 mW
Minimum Operating Temperature
- 40 C
Output Type
Open Drain
Propagation Delay Time
150 ns @ 5 V or 75 ns @ 10 V
Number Of Lines (input / Output)
6 / 6
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MM74C906M
Manufacturer:
Fairchild Semiconductor
Quantity:
668
Part Number:
MM74C906M
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
MM74C906MX
Manufacturer:
FAI
Quantity:
20 000
© 2004 Fairchild Semiconductor Corporation
MM74C906M
(Note 1)
MM74C906N
MM74C906
Hex Open Drain N-Channel Buffers
General Description
The MM74C906 buffer employs monolithic CMOS technol-
ogy in achieving open drain outputs. The MM74C906 con-
sists of six inverters driving six N-channel devices. The
open drain feature of these buffers makes level shifting or
wire AND and wire OR functions by just the addition of pull-
up or pull-down resistors. All inputs are protected from
static discharge by diode clamps to V
Ordering Code:
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignments for DIP and SOIC
Package Number
Top View
M14A
N14A
CC
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
and to ground.
DS005911
Features
Logic Diagram
Wide supply voltage range:
Guaranteed noise margin: 1V
High noise immunity: 0.45 V
High current sourcing and sinking open drain outputs
Package Description
October 1987
Revised January 2004
CC
3V to 15V
(typ.)
www.fairchildsemi.com

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