74LVT241PW,112 NXP Semiconductors, 74LVT241PW,112 Datasheet
74LVT241PW,112
Specifications of 74LVT241PW,112
74LVT241PW
935210110112
Related parts for 74LVT241PW,112
74LVT241PW,112 Summary of contents
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V octal buffer/line driver; 3-state Rev. 03 — 7 May 2008 1. General description The 74LVT241 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. This device is an octal ...
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... NXP Semiconductors 4. Functional diagram 1A0 2 1A1 4 1A2 6 1A3 8 1OE 1 2A0 17 2A1 15 2A2 13 2A3 11 2OE 19 Fig 1. Logic symbol 74LVT241_3 Product data sheet 1Y0 18 1Y1 16 1Y2 14 1Y3 12 2Y0 3 2Y1 5 2Y2 7 2Y3 9 mna772 Fig 2. Rev. 03 — 7 May 2008 74LVT241 3.3 V octal buffer/line driver; 3-state ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 1 1OE 2 1A0 2Y0 3 1A1 4 5 2Y1 74LVT241 1A2 6 2Y2 7 8 1A3 9 2Y3 GND 10 001aah734 Fig 3. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin 1OE 1 1A0 to 1A3 2A0 to 2A3 ...
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... NXP Semiconductors 6. Functional description Table 3. Function table Inputs 1OE 2OE [ HIGH voltage level LOW voltage level Don’t care High impedance “OFF” state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter I LOW-level output current OL T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); T Symbol Parameter V input clamping voltage ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); T Symbol Parameter I supply current CC I additional supply current CC C input capacitance I C input/output capacitance I/O [1] All typical values are measured at T [2] Unused pins GND. CC [3] This is the bus hold overdrive current required to force the input to the opposite logic state. ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t OFF-state to LOW propagation delay 1OE to 1Yn; see PZL t HIGH to OFF-state propagation delay 1OE to 1Yn; see PHZ t LOW to OFF-state propagation delay 1OE to 1Yn; see PLZ ...
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... NXP Semiconductors 1OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH See Table 8 for measurement points. V and V are typical output voltage levels that occur with the output load Fig 6. 3-state output enable and disable times 2OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF ...
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... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for switching times Table 9. Test data Input ...
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... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 10. Package outline SOT339-1 (SSOP20) ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... Release date 74LVT241_3 20080507 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • DHVQFN20 package added 74LVT241_2 19980219 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Revision history ...