74LVT245PW,112 NXP Semiconductors, 74LVT245PW,112 Datasheet

IC TRANSCVR TRI-ST 8BIT 20TSSOP

74LVT245PW,112

Manufacturer Part Number
74LVT245PW,112
Description
IC TRANSCVR TRI-ST 8BIT 20TSSOP
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT245PW,112

Logic Type
Transceiver, Non-Inverting
Package / Case
20-TSSOP
Number Of Elements
1
Number Of Bits Per Element
8
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Logic Family
74LVT
Number Of Channels Per Chip
8
Input Level
LVTTL
Output Level
LVTTL
Output Type
3-State
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Propagation Delay Time
2.4 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Function
Bus Transceiver
Input Bias Current (max)
12000 uA
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Polarity
Non-Inverting
Number Of Circuits
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1595-5
74LVT245PW
935175550112
1. General description
2. Features
3. Ordering information
Table 1.
Type number
74LVT245D
74LVT245DB
74LVT245PW
74LVT245BQ
Ordering information
Package
Temperature range Name
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
The 74LVT245 is a high-performance BiCMOS product designed for V
3.3 V.
This device is an octal transceiver featuring non-inverting 3-state bus compatible outputs
in both send and receive directions. The control function implementation minimizes
external timing requirements. It features an output enable (OE) input for easy cascading
and a direction (DIR) input for direction control.
I
I
I
I
I
I
I
I
I
I
I
74LVT245
3.3 V octal transceiver with direction pin (3-state)
Rev. 03 — 8 May 2008
3-state buffers
Octal bidirectional bus interface
Input and output interface capability to systems at 5 V supply
TTL input and output switching levels
Output capability: +64 mA/ 32 mA
Latch-up protection exceeds 500 mA per JESD78 class II level A
ESD protection:
Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs
Live insertion/extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
N
N
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
SO20
SSOP20
TSSOP20
DHVQFN20 plastic dual in-line compatible thermal enhanced very
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
thin quad flat package; no leads; 20 terminals;
body 2.5
4.5
0.85 mm
Product data sheet
CC
operation at
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1

Related parts for 74LVT245PW,112

74LVT245PW,112 Summary of contents

Page 1

V octal transceiver with direction pin (3-state) Rev. 03 — 8 May 2008 1. General description The 74LVT245 is a high-performance BiCMOS product designed for V 3.3 V. This device is an octal transceiver featuring non-inverting 3-state bus ...

Page 2

... NXP Semiconductors 4. Functional diagram DIR Fig 1. Logic diagram 74LVT245_3 Product data sheet 3.3 V octal transceiver with direction pin (3-state mna174 Fig 2. IEC logic symbol Rev. 03 — 8 May 2008 74LVT245 3EN1 3EN2 mna175 © NXP B.V. 2008. All rights reserved ...

Page 3

... NXP Semiconductors 5. Pinning information 5.1 Pinning DIR 74LVT245 GND Fig 3. Pin configuration for SO20 and (T)SSOP20 5.2 Pin description Table 2. Pin description Symbol Pin DIR GND 18, 17, 16, 15, 14, 13, 12 74LVT245_3 Product data sheet 3.3 V octal transceiver with direction pin (3-state) ...

Page 4

... NXP Semiconductors 6. Functional description Table 3. Function selection Inputs OE DIR [ HIGH voltage level LOW voltage level don’t care high impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...

Page 5

... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter I LOW-level output current OL T ambient temperature amb t/ V input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter V input clamping voltage ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC I additional supply current CC C input capacitance I C input/output capacitance I/O [1] All typical values are measured at V [2] Unused pins GND. CC [3] This parameter is valid for any transition time of 100 ms is permitted ...

Page 7

... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter t LOW to OFF-state propagation delay see PLZ [1] Typical values are measured at T 11. Waveforms See Table 8 for measurement points V and V are typical output voltage levels that occur with the output load. ...

Page 8

... NXP Semiconductors Table 8. Measurement points V Input 2 3.6 V GND to 2.7 V Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 7. Test circuit for switching times Table 9 ...

Page 9

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 10

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 9. ...

Page 11

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 12

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 13

... Release date 74LVT245_3 20080508 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering information” 74LVT245_2 ...

Page 14

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 15

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 Revision history ...

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