TAS5508C

Manufacturer Part NumberTAS5508C
ManufacturerTexas Instruments
TAS5508C datasheet
 


Specifications of TAS5508C

Audio Output Channels (pwm)(#)8Dynamic Range(db)110
Data Resolution16,20,24Digital Supply (up To 5 V)(min)(v)3
Digital Supply (up To 5 V)(max)(v)3.6Fs(min)(khz)32
Fs(max)(khz)192Pwm Headphone OutputYes
Serial InterfaceI2S, R, LVolume ControlYes
Loudness CompensationYesMuteYes
OutputPWMEqYes
Bass/treble Tone ControlYes  
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TAS5508C
8-Channel Digital Audio PWM Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES257
September 2010

TAS5508C Summary of contents

  • Page 1

    ... TAS5508C 8-Channel Digital Audio PWM Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES257 September 2010 ...

  • Page 2

    ... Threshold Parameter Computation 2.10.2.2 Offset Parameter Computation 2.10.2.3 Slope Parameter Computation ............................................................................................................... 2.11 Output Mixer ........................................................................................................................ 2.12 PWM 2.12.1 DC Blocking (High-Pass Enable/Disable) 2.12.2 De-Emphasis Filter 2.12.3 Power-Supply Volume Control (PSVC) 2.12.4 AM Interference Avoidance 3 TAS5508C Controls and Status ....................................................................................................... 2 3 Status Registers 3.1.1 General Status Register (0x01) 2 Contents Contents ............................................................................................ .................................................................................................. ......................................................................................... ........................................................................................... ................................................................................................ ...................................................................................... ................................................................................................... ...

  • Page 3

    ... Error Status Register (0x02) 3.2 TAS5508C Pin Controls 3.2.1 Reset (RESET) 3.2.2 Power Down (PDN) 3.2.3 Back-End Error (BKND_ERR) 3.2.4 Speaker/Headphone Selector (HP_SEL) .................................................................................................... 3.2.5 Mute (MUTE) 3.3 Device Configuration Controls 3.3.1 Channel Configuration Registers 3.3.2 Headphone Configuration Registers 3.3.3 Audio System Configurations 3.3.3.1 Using Line Outputs in 6-Channel Configurations 3.3.4 Recovery from Clock Error 3 ...

  • Page 4

    ... TAS5508C SLES257 – SEPTEMBER 2010 4.8.3 Right-Justified Timing Serial-Control Interface (Slave Address 0x36) .................................................................................................... 2 5.1 General I C Operation 5.2 Single- and Multiple-Byte Transfers .......................................................................................................... 5.3 Single-Byte Write ........................................................................................................ 5.4 Multiple-Byte Write 5.5 Incremental Multiple-Byte Write .......................................................................................................... 5.6 Single-Byte Read ........................................................................................................ 5.7 Multiple-Byte Read 2 6 Serial-Control I C Register Summary 7 Serial-Control Interface Register Definitions 7 ...

  • Page 5

    ... PSVC Range Register (0xDF) 7.37 General Control Register (0xE0) 7.38 Incremental Multiple-Write Append Register (0xFE) 8 TAS5508C Example Application Schematic Copyright © 2010, Texas Instruments Incorporated ........................................................................................... ........................................................................................ .................................................................. ......................................................................... TAS5508C SLES257 – SEPTEMBER 2010 101 Contents 5 ...

  • Page 6

    ... Output Mixers 2-19 De-Emphasis Filter Characteristics 2-20 Power-Supply and Digital Gains (Log Space) 2-21 Power-Supply and Digital Gains (Linear Space) 2-22 Block Diagrams of Typical Systems Requiring TAS5508C Automatic AM Interference-Avoidance Circuit 4-1 Slave Mode Serial Data Interface Timing ............................................................................................................ 4-2 SCL and SDA Timing 4-3 Start and Stop Conditions Timing ...

  • Page 7

    ... Values Set During Reset 3-3 Device Outputs During Power Down 3-4 Device Outputs During Back-End Error 3-5 Description of the Channel Configuration Registers (0x05 to 0x0C) 3-6 Recommended TAS5508C Configurations for Texas Instruments Power Stages 3-7 Audio System Configuration (General Control Register 0xE0) ..................................................................................................... 3-8 Volume Ramp Rates in ms 3-9 Interchannel Delay Default Values ...

  • Page 8

    ... TAS5508C SLES257 – SEPTEMBER 2010 7-31 Output Mixer Register Format (Lower 4 Bytes) 7-32 Volume Biquad Register Format (Default = All-Pass) 7-33 Volume Gain Update Rate (Slew Rate) 7-34 Treble and Bass Gain Step Size (Slew Rate) ........................................................................................................ 7-35 Volume Register Format 7-36 Master and Individual Volume Controls .......................................................................................................... 7-37 Channel 8 (Subwoofer) 7-38 Channels 6 and 5 (Right and Left Lineout in 6-Channel Configuration ...

  • Page 9

    ... Flat Noise Floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Rates – Digital De-Emphasis for 32-, 44.1-, and 48-kHz Data Rates – Flexible Automute Logic With Programmable Threshold and Duration for Noise-Free TAS5508C SLES257 – SEPTEMBER 2010 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 10

    ... The TAS5508C is designed to interface seamlessly with most audio digital signal processors. The TAS5508C automatically adjusts control configurations in response to clock and data rate changes and idle conditions. This enables the TAS5508C to provide an easy-to-use control interface with relaxed timing requirements. ...

  • Page 11

    ... AVSS AVDD DVSS DVDD VRD_PLL VRA_PLL VBGAP AVDD_REF AVSS_PLL AVDD_PLL VR_PLL Figure 1-1. TAS5508C Functional Structure Copyright © 2010, Texas Instruments Incorporated Output Control 8 2 Crossbar Mixer 8 8 Crossbar Mixer DAP Control System Control Clock, PLL, and Serial Data I/F Submit Documentation Feedback ...

  • Page 12

    ... TAS5508C SLES257 – SEPTEMBER 2010 1.3 TAS5508C System Diagrams Typical applications for the TAS5508C are 6- to 8-channel audio systems such as DVD or AV receivers. Figure 1-2 shows the basic system diagram of the DVD receiver. Power Supply DVD Loader Figure 1-2. Typical TAS5508C Application (DVD Receiver) ...

  • Page 13

    ... Figure 1-3. Recommended TAS5508C and TAS5121 Channel Configuraton Copyright © 2010, Texas Instruments Incorporated TAS5508C Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 Introduction PWM 13 ...

  • Page 14

    ... TAS5508C SLES257 – SEPTEMBER 2010 14 Introduction PWM Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 15

    ... PLASTIC 64-PIN PQFP (PN) Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 VR_PWM 48 PWM_P_4 47 46 PWM_M_4 45 PWM_P_3 44 PWM_M_3 PWM_P_2 43 PWM_M_2 42 PWM_P_1 41 40 PWM_M_1 39 VALID 38 DVSS BKND_ERR 37 DVDD 36 DVSS 35 DVSS 34 33 VR_DIG P0010-01 TAS5508CPAG Description 15 ...

  • Page 16

    ... PWM 6 output (differential –) PWM 7 (lineout L) output (differential –) PWM 8 (lineout R) output (differential –) PWM 1 output (differential +) PWM 2 output (differential +) PWM 3 output (differential +) PWM 4 output (differential +) Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com DESCRIPTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 17

    ... System reset input, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5508C to its default conditions, sets the valid output low, and places the PWM in the hard mute (M) state. Master volume is immediately set to full attenuation ...

  • Page 18

    ... The regulators can also be turned off when terminals RESET and PDN are both low. 2.2.2 Clock, PLL, and Serial Data Interface The TAS5508C is a clocked slave-only device that requires the use of an external 13.5-MHz crystal. It accepts MCLK, SCLK, and LRCLK as inputs only. The TAS5508C uses the external crystal to provide a time base for: • ...

  • Page 19

    ... RECEIVE SERIAL DATA FORMAT Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5508C accepts 16-, 20-, or 24-bit serial data at 32, 38, 44.1, 48, 88.2, 96, 176.4, or 192 kHz in left-justified, I Data is input using a 64-Fs SCLK clock and an MCLK rate of 128, 192, 256, 384, 512, or 768 Fs maximum of 50 MHz ...

  • Page 20

    ... To support efficiently the processing requirements of both multichannel 32-kHz to 96-kHz data and the 2-channel 176.4-kHz and 192-kHz data, the TAS5508C has separate audio-processing features for 32-kHz to 96-kHz data rates and for 176.4 kHz and 192 kHz. See processing feature sets ...

  • Page 21

    ... Note that the I the designer configure the TAS5508C. Figure 2-2 shows the TAS5508C architecture for Fs = 176.4 kHz 192 kHz. Note that only channels 1, 2, and 8 contain all the features. Channels 3–7 are pass-through except for master volume control. Figure 2-3 shows TAS5508C detailed channel processing. The output mixer is 8× ...

  • Page 22

    ... SDIN3-L (LBS) E (0x82− Crossbar SDIN3-R (RBS) F 0x83) Input Mixer SDIN4-L (C) G (1) SDIN4-R (LFE) H Coeff = 0 (lin), (I (1) Default inputs Figure 2-1. TAS5508C DAP Architecture With I 22 Description Master Vol 7 DAP 1 Bass and BQ Treble 1 (0x51− (0xDA− 0x57) 0xDD) Master Vol 7 DAP 2 ...

  • Page 23

    ... SDIN3-L (LBS) ´ E Crossbar SDIN3-R (RBS) F Input Mixer SDIN4-L (C) G (1) H SDIN4-R (LFE) (1) Default inputs Figure 2-2. TAS5508C Architecture With I Copyright © 2010, Texas Instruments Incorporated Master Vol (0xD9) Bass and 4BQ DAP 1 Treble 1 (0x51– Volume (0xDA– 0x54) (0xD1) 0xDD) ...

  • Page 24

    ... The architecture of the TAS5508C is contained in ROM resources within the TAS5508C and cannot be altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I interface, provide a user with the flexibility to set the TAS5508C to a configuration that achieves system-level goals. ...

  • Page 25

    ... Digit Coefficient Coefficient Coefficient Digit 6 Digit 5 Digit 4 Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 M0007-01 Figure Figure 2-5 applied to −4 −23 2 Bit 2 Bit −4 − M0008-01 Figure 2-6. Fraction Digit 6 ...

  • Page 26

    ... Bit Figure 2-8. Alignment of 5.23 Coefficient in 32-Bit I Two 32-bit words must be sent over the I TAS5508C. The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I word is shown in Figure 2-9. 26 Description Figure 2-7. Figure 2-7. 25.23 Format 22 0 − ...

  • Page 27

    ... Similarly, the TAS5508C carries additional precision in the form of overflow bits to permit the value of intermediate calculations to exceed the input precision without clipping. The TAS5508C advanced digital ...

  • Page 28

    ... For 32-kHz to 96-kHz data, the TAS5508C provides 56 biquads across the eight channels (seven per channel). For 176.4-kHz and 192-kHz data, the TAS5508C has 21 biquads across the three channels (seven per channel). All of the biquad filters are second-order direct form I structure. ...

  • Page 29

    ... Bass and Treble Controls From 32-kHz to 96-kHz data, the TAS5508C has four bass and treble tone controls. Each control has a ±18-dB control range with selectable corner frequencies and second-order slopes. These controls operate four channel groups: • and C (channels 1, 2, and 7) • ...

  • Page 30

    ... The TAS5508C has individual channel automute controls that are enabled via the I separate detectors can trigger the automute: • Input automute: All channels are muted when all 8 inputs to the TAS5508C are less in magnitude than the input threshold value for a programmable amount of time. 30 ...

  • Page 31

    ... Bits in DSPE Representation The automute state is exited when the TAS5508C receives one sample that is greater than the output threshold. The output threshold can be one of two values: • ...

  • Page 32

    ... Loudness Example Problem: Due to the Fletcher-Munson phenomena, we want to compensate for low-frequency attenuation near 60 Hz. The TAS5508C provides a loudness transfer function with EQ gain = 6, EQ center frequency = 60 Hz, and EQ bandwidth = 60 Hz. Solution: Using Texas Instruments ALE TAS5508C DSP tool, Matlab™, or other signal-processing tool, ...

  • Page 33

    ... The mixer output is the DRC-adjusted audio data. There are two distinct DRC blocks in the TAS5508C. DRC1 services channels 1–7 in the 8-channel mode and channels 1–4 and 7 in the 6-channel mode. This DRC computes rms estimates of the audio data streams on all channels that it controls ...

  • Page 34

    ... TAS5508C SLES257 – SEPTEMBER 2010 All of the TAS5508C default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 2-8 shows the recommended time constants and their hex values. If the user wants to implement other DRC functions, Texas Instruments recommends using the automatic loudspeaker equalization (ALE) tool available from Texas Instruments ...

  • Page 35

    ... Copyright © 2010, Texas Instruments Incorporated Region Region 1:1 Transfer Function Implemented Transfer Function O2 T2 Figure 2-17 are defined by three sets of programmable coefficients: CAUTION Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 M0014-01 Description 35 ...

  • Page 36

    ... Description * window F n n(1 * aa) S Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com * n(1 * ad) S Copyright © 2010, Texas Instruments Incorporated ...

  • Page 37

    ... For example, to achieve a boost threshold T1, the I O1 must be: Copyright © 2010, Texas Instruments Incorporated + | For ( | –6.0206T INPUT SUB_ADDRESS_ENTRY T1 + SUB_ADDRESS_ENTRY *6.0206 O ) 24.0824 dB DESIRED O + INPUT 6.0206 Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 *64 + 10. coefficient value entered for Description 37 ...

  • Page 38

    ... DRC. As the input increases in volume, the output decreases in volume. 2.11 Output Mixer The TAS5508C provides an 8×2 output mixer for channels and 6. For channels 7 and 8, the TAS5508C provides an 8×3 output mixer. These mixers allow each output to be any ratio of any two (or three) signal-processed channels ...

  • Page 39

    ... Output N 2.12 PWM The TAS5508C has eight channels of high-performance digital PWM modulators that are designed to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge-tied load) configurations. The TAS5508C device uses noise-shaping and sophisticated, error-correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The TAS5508C uses an AD1 PWM modulation scheme combined with a fifth-order noise shaper to provide a 102-dB SNR from kHz ...

  • Page 40

    ... Figure 2-19. De-Emphasis Filter Characteristics 2.12.3 Power-Supply Volume Control (PSVC) The TAS5508C supports volume control both by conventional digital gain/attenuation and by a combination of digital and analog gain/attenuation. Varying the H-bridge power-supply voltage performs the analog volume control function. The benefits of using power-supply volume control (PSVC) are reduced idle channel noise, improved signal resolution at low volumes, increased dynamic range, and reduced radio frequency emissions at reduced power levels ...

  • Page 41

    ... AM interference-avoidance circuit provides a flexible system solution for a wide variety of digital audio architectures. During AM reception, the TAS5508C adjusts the radiated emissions to provide an emission-clear zone for the tuned AM frequency. The inputs to the TAS5508C for this operation are the tuned AM frequency, the IF frequency, and the sample rate. The sample rate is automatically detected. ...

  • Page 42

    ... TAS5508C SLES257 – SEPTEMBER 2010 Analog Receiver Figure 2-22. Block Diagrams of Typical Systems Requiring TAS5508C Automatic AM 42 Description ADC Audio TAS5508C PCM1802 DSP Audio DSP Provides the Master and Bit Clocks Digital Audio TAS5508C Receiver DSP The Digital Receiver or the Audio DSP ...

  • Page 43

    ... MUTE 3.2.1 Reset (RESET) The TAS5508C is placed in the reset mode either by the power-up reset circuitry when power is applied setting the RESET terminal low. RESET is an asynchronous control signal that restores the TAS5508C to the hard mute state (M). Master volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without an MCLK input ...

  • Page 44

    ... Ch1 and Ch2 sum in subwoofer (5508) Bass and treble bypass Bass and treble inline DRC bypass (5508) DRC inline (5508) DRC (5508) 44 TAS5508C Controls and Status SIGNAL STATE Signal input (not driven) Table 3-2. Values Set During Reset SETTING Not valid Disabled ...

  • Page 45

    ... I 3.2.2 Power Down (PDN) The TAS5508C can be placed into the power-down mode by holding the PDN terminal low. When the power-down mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation (there is no ramp down) ...

  • Page 46

    ... TAS5508C SLES257 – SEPTEMBER 2010 The crystal time base allows the TAS5508C to determine the CLK rates. Once these rates are determined, the TAS5508C unmutes the audio. 3.2.3 Back-End Error (BKND_ERR) Back-end error is used to provide error management for back-end error conditions. Back-end error is a level-sensitive signal ...

  • Page 47

    ... This provides better control of each power stage. D5 Determines if the power stage needs the TAS5508C VALID pin to go low to mute the power stage. Some power stages can be muted by a combination of PWM signals. For these devices recommended to set this bit low, because the VALID pin is shared for power stages ...

  • Page 48

    ... Audio System Configurations The TAS5508C can be configured to comply with various audio systems: 5.1-channel system, 6-channel system, 7.1-channel system, and 8-channel system. The audio system configuration is set in the general control register (0xE0). Bits D31–D4 must be zero and D0 is don't care ...

  • Page 49

    ... The operation of the channel-5 and -6 biquads is unaffected by the 6-/8-channel configuration setting. 3.3.4 Recovery from Clock Error The TAS5508C can be set either to perform a volume ramp up during the recovery sequence of a clock error or simply to come up in the last state (or desired state if a volume or tone update was in progress). ...

  • Page 50

    ... TAS5508C output needs to get ready for the next ontime period. The maximum possible modulation is then set by the power stage requirements. All Texas Instruments power stages need maximum modulation to be 97.7%. This is also the default setting of the TAS5508C. Default settings can be changed in the modulation index register (0x16). ...

  • Page 51

    ... However, there is no constraint as to the phase relationship of these signals. The TAS5508C accepts a 64 × Fs SCLK rate and a 1 × Fs LRCLK. If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last reset, the TAS5508C senses a clock error and resynchronizes the clock timing. ...

  • Page 52

    ... While a mute is active, the commanded channels are muted. When a channel is unmuted, the volume level goes to the last commanded volume setting that has been received for that channel. If MCLK or SCLK is stopped, the TAS5508C performs a bank-switch operation. If the clocks start up once the manual bank-switch command has been received, the bank-switch operation is performed during the 5-ms, silent-start sequence ...

  • Page 53

    ... Bank-Switching Example 2 Problem: The audio system uses all of the sample rates supported by the TAS5508C. How can the automatic bank switching be set up to handle this situation? Strategy: Use the TAS5508C bank-switching feature to allow for managing and switching three banks associated with sample rates as follows: • ...

  • Page 54

    ... TAS5508C SLES257 – SEPTEMBER 2010 54 TAS5508C Controls and Status Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 55

    ... RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL. (3) VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM (4) VREF is a 1.8-V supply derived from regulators internal to the TAS5508C chip. VREF is on terminals VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used to source power to external devices ...

  • Page 56

    ... MCLK minimum high time MCLK minimum low time LRCLK allowable drift before LRCLK reset External PLL filter capacitor C1 External PLL filter capacitor C2 External PLL filter resistor R External VRA_PLL decoupling (1) See the TAS5508C Example Application Schematic, 56 Electrical Specifications TEST CONDITIONS (1) tolerant I = –4 mA ...

  • Page 57

    ... Figure 4-1. Slave Mode Serial Data Interface Timing Copyright © 2010, Texas Instruments Incorporated TEST CONDITIONS pF,SCLK = 64 × su1 Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 MIN TYP MAX UNIT 2.048 12.288 MHz ...

  • Page 58

    ... Condition Figure 4-3. Start and Stop Conditions Timing 58 Electrical Specifications TEST CONDITIONS No wait states t w(L) t su1 Figure 4-2. SCL and SDA Timing su2 su3 Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com MIN MAX 400 0.6 1.3 300 300 100 0 1.3 0.6 0.6 0.6 400 ...

  • Page 59

    ... M-State t < 300 s m p(DMSTATE) Copyright © 2010, Texas Instruments Incorporated PARAMETER Figure 4-4. Reset Timing PARAMETER t su Figure 4-5. Power-Down Timing Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 MIN TYP MAX UNIT 370 ns 400 None ...

  • Page 60

    ... M-State Normal Operation 60 Electrical Specifications t w(ER) t p(valid_high) t p(valid_low) Figure 4-6. Error Recovery Timing Section 7.29. t d(VOL) Figure 4-7. Mute Timing Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com MIN TYP MAX UNIT 350 None ns <100 ms – interval Normal Operation T0031-01 MIN TYP ...

  • Page 61

    ... M-State Copyright © 2010, Texas Instruments Incorporated Defined by rate setting Section 7.29. t d(VOL) t (SW) t d(VOL) t (SW) Figure 4-8. HP_SEL Timing Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 MIN MAX UNIT 350 None ns ( d(VOL) t d(VOL) T0033-01 ...

  • Page 62

    ... There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508C masks unused trailing data bit positions. 2 ...

  • Page 63

    ... LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 × used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508C masks unused trailing data bit positions. ...

  • Page 64

    ... Fs is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit data) after LRCLK toggles mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS5508C masks unused leading data bit positions. ...

  • Page 65

    ... During multiple-byte read operations, the TAS5508C responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges particular subaddress does not contain 32 bits, the unused bits are read as logic 0. ...

  • Page 66

    ... TAS5508C expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop command (or another start command) is received, the data received is discarded. Similarly write command is received for a mixer coefficient, the TAS5508C expects to receive one 32-bit word. ...

  • Page 67

    ... The operation is terminated due to an error condition, and the data is flushed: ( new subaddress is written to the TAS5508C before the correct number of bytes are written. (b) If more or fewer than four bytes are data written at the beginning or during any of the append operations ...

  • Page 68

    ... SLES257 – SEPTEMBER 2010 5.7 Multiple-Byte Read A multiple-byte, data-read transfer is identical to a single-byte, data-read transfer except that multiple data bytes are transmitted by the TAS5508C to the master device, as shown in data byte, the master device responds with an acknowledge bit after receiving each data byte. Start Condition ...

  • Page 69

    ... Serial-Control I C Register Summary The TAS5508C slave address is 0x36. See Serial-Control Interface Register Definitions, complete bit definitions. Note that u indicates unused bits. 2 TOTAL I C REGISTER FIELDS BYTES SUBADDRESS 0x00 1 Clock control register 0x01 1 General status register 0x02 1 Error status register ...

  • Page 70

    ... DRC2 threshold (T1) – lower 4 bytes 0x0B, 0x20, 0xE2, 0xB2 DRC2 threshold (T2) – upper 2 bytes 0x00, 0x00, 0x00, 0x00 DRC2 threshold (T2) – lower 4 bytes 0x06, 0xF9, 0xDE, 0x58 Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com DEFAULT STATE Copyright © 2010, Texas Instruments Incorporated ...

  • Page 71

    ... Ch1 volume 0 dB Ch2 volume 0 dB Ch3 volume 0 dB Ch4 volume 0 dB Ch5 volume 0 dB Ch6 volume 0 dB Ch7 volume 0 dB Ch8 volume 0 dB Serial-Control I Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 DEFAULT STATE Register Summary ...

  • Page 72

    ... Use BCD-tuned frequency Set PSVC control range 12-dB control range 6- or 8-channel configuration, PSVC 8-channel configuration enable Power-supply volume control disabled Reserved Special register N/A Reserved Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com DEFAULT STATE Copyright © 2010, Texas Instruments Incorporated ...

  • Page 73

    ... Clock register is not valid (read-only – – – Clip indicator – – – Bank switching busy Identification code for TAS5508C Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION FUNCTION Serial-Control Interface Register Definitions 73 ...

  • Page 74

    ... Unmute threshold equal to input threshold de-emphasis 0 1 De-emphasis for kHz 1 0 De-emphasis for Fs = 44.1 kHz 1 1 De-emphasis for kHz Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION Function Function Copyright © 2010, Texas Instruments Incorporated ...

  • Page 75

    ... Do not remap Hi-Z state to low-low state – BE5111BsMute – 1 Remap Hi-Z state to low-low state 2 C interface. WORD LENGTHS D7–D4 16 0000 20 0000 24 0000 Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION FUNCTION ...

  • Page 76

    ... Soft mute channel 6 – – – – Soft mute channel 7 – – – – Soft mute channel Unmute All Channels Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com ...

  • Page 77

    ... Set input automute threshold less than bit 13 – – – Set input automute threshold less than bit 14 – – – Set input automute threshold less than bit 15 Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION Serial-Control Interface Register Definitions 77 ...

  • Page 78

    ... Set back-end reset period Set back-end reset period Set back-end reset period Set back-end reset period Set back-end reset period 10 ms Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 79

    ... Default value for channel 7 = –8 Default value for channel Minimum absolute offset, 0 DCLK cycles, default for channel Maximum absolute offset, 255 DCLK cycles Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 MIN WIDTH MODULATION [DCLKs] INDEX 2 99.2% 4 98.4% 6 97. ...

  • Page 80

    ... Default Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 81

    ... SDIN4-right (Ch8 input mixer 3 coefficient (default = 0) u[31:28], H_3[27:24], H_3[23:16], H_3[15:8], H_3[7:0] Serial-Control Interface Register Definitions Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 DEFAULT STATE 0x00, 0x80, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 ...

  • Page 82

    ... SDIN4-left (Ch7 input mixer 6 coefficient (default = 0) u[31:28], G_6[27:24], G_6[23:16], G_6[15:8], G_6[7:0] SDIN4-right (Ch8 input mixer 6 coefficient (default = 0) u[31:28], H_6[27:24], H_6[23:16], H_6[15:8], H_6[7:0] Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com DEFAULT STATE 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 ...

  • Page 83

    ... SDIN4-right (Ch8 input mixer 8 coefficient (default = 1) u[31:28], H_8[27:24], H_8[23:16], H_8[15:8], H_8[7:0] Serial-Control Interface Register Definitions Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 DEFAULT STATE 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 ...

  • Page 84

    ... Table 7-19 for bit definition. Ch8 biquads 1–7. See Table 7-19 for bit definition. Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com DEFAULT STATE 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00 0x00, 0x80, 0x00, 0x00 ...

  • Page 85

    ... O[31:24], O[23:16], O[15:8], O[7:0] ) u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] ) u[31:28], b1[27:24], b1[23:16], b1[15:8], b1[7:0] ) u[31:28], b2[27:24], b2[23:16], b2[15:8], b2[7:0] ) u[31:28], a1[27:24], a1[23:16], a1[15:8], a1[7:0] ) u[31:28], a2[27:24], a2[23:16], a2[15:8], a2[7:0] Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 DEFAULT GAIN COEFFICIENT VALUES DECIMAL HEX 1.0 0x00, 0x80, 0x00, 0x00 0.0 0x00, 0x00, 0x00, 0x00 0.0 0x00, 0x00, 0x00, 0x00 0.0 0x00, 0x00, 0x00, 0x00 0.0 0x00, 0x00, 0x00, 0x00 ...

  • Page 86

    ... Channel 7 (node q): No DRC – Channel 7 (node q): Pre-volume DRC – Channel 7 (node q): Post-volume DRC – Channel 7 (node q): No DRC Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 87

    ... A[27:24], A[23:16], A[15:8], A[7:0] u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 1–A[7:0] u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 1–D[7:0] Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 DEFAULT STATE 0x00, 0x00, 0x88, 0x3F 0x00, 0x7F, 0x77, 0xC0 0x00, 0x00, 0x00, 0x00 0x0B, 0x20, 0xE2, 0xB2 0x00, 0x00, 0x00, 0x00 ...

  • Page 88

    ... A[27:24], A[23:16], A[15:8], A[7:0] u[31:28], 1–A[27:24], 1–A[23:16], 1–A[15:8], 1–A[7:0] u[31:28], D[27:24], D[23:16], D[15:8], D[7:0] u[31:28], 1–D[27:24], 1–D[23:16], 1–D[15:8], 1–D[7:0] CONTENTS Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com DEFAULT STATE 0x00, 0x00, 0x88, 0x3F 0x00, 0x7F, 0x77, 0xC0 0x00, 0x00, 0x00, 0x00 0x0B, 0x20, 0xE2, 0xB2 0x00, 0x00, 0x00, 0x00 ...

  • Page 89

    ... Selected channel gain (continued) D10 D9 D8 G10 G9 G8 Selected channel gain (continued Selected channel gain (lower 8 bits) Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION Serial-Control Interface Register Definitions 89 ...

  • Page 90

    ... Selected channel gain (lower 8 bits) D26 D25 D24 Select channel 1 to output mixer Select channel 2 to output mixer Select channel 3 to output mixer Select channel 4 to output mixer Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION Copyright © ...

  • Page 91

    ... G8 Selected channel gain (continued Selected channel gain (lower 8 bits) Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION FUNCTION FUNCTION FUNCTION DEFAULT GAIN COEFFICIENT VALUES DECIMAL HEX 1.0 0x00, 0x80, 0x00, 0x00 0.0 0x00, 0x00, 0x00, 0x00 ...

  • Page 92

    ... Table 7-35. Volume Register Format D26 D25 D24 Unused bits D18 D17 D16 Unused bits D10 D9 D8 V10 V9 V8 Volume Volume Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 93

    ... TO –126 –126.43 –126.25 –126.68 –126.5 –126.93 –126.75 –127.19 –127 –127.44 Mute Mute TO Mute Mute Serial-Control Interface Register Definitions Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 ACTUAL 17.81 17.56 17.31 17.06 16.81 16.56 16.31 16.05 15.8 15.55 15.3 15.05 14.8 14.55 14.3 14.05 1 0.75 0.5 0.25 0 –0.25 –0.5 –0.75 – ...

  • Page 94

    ... Bass filter set Bass filter set Bass filter set Bass filter set Reserved Reserved Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 95

    ... Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION DEFAULT STATE 0x12, 0x12, 0x12, 0x12 ADJUSTMENT (dB) –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 –11 –12 –13 – ...

  • Page 96

    ... Treble filter set Reserved Reserved change Treble filter set Treble filter set 2 Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 97

    ... Table 7-49. AM Mode Register Format D26 D25 D24 Unused bits Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 FUNCTION DEFAULT STATE 0x12, 0x12, 0x12, 0x12 ADJUSTMENT (dB) –1 –2 –3 –4 –5 –6 –7 –8 –9 – ...

  • Page 98

    ... D9 D8 B10 B9 B8 Binary frequency (upper 3 bits Default value Binary frequency (lower 8 bits Default value Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION FUNCTION Copyright © 2010, Texas Instruments Incorporated ...

  • Page 99

    ... Copyright © 2010, Texas Instruments Incorporated FUNCTION FUNCTION 8-channel configuration 6-channel configuration Power-supply volume control disabled Power-supply volume control enabled Subwoofer part of PSVC Subwoofer separate from PSVC Serial-Control Interface Register Definitions Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 99 ...

  • Page 100

    ... TAS5508C SLES257 – SEPTEMBER 2010 100 Serial-Control Interface Register Definitions Submit Documentation Feedback Product Folder Link(s): TAS5508C www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 101

    ... TAS5508C Example Application Schematic The following page contains an example application schematic for the TAS5508C. Copyright © 2010, Texas Instruments Incorporated TAS5508C Example Application Schematic Submit Documentation Feedback Product Folder Link(s): TAS5508C TAS5508C SLES257 – SEPTEMBER 2010 101 ...

  • Page 102

    Phono socket J950 LINE OUTPUT Phono socket J951 GND J900 4 3 HEADPHONE OUTPUT 2 1 Mini-Jack (3.5mm) C C10 R10 R11 10nF 200R 200R C11 C12 100nF ...

  • Page 103

    ... Orderable Device (1) Package Type Package Status TAS5508CPAG ACTIVE TQFP TAS5508CPAGR ACTIVE TQFP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 104

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TAS5508CPAGR TQFP PAG PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 64 1500 330.0 24.4 13.0 Pack Materials-Page 1 21-Sep-2010 Pin1 (mm) (mm) (mm) (mm) Quadrant 13.0 1.5 16.0 24.0 Q2 ...

  • Page 105

    ... Device Package Type TAS5508CPAGR TQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PAG 64 1500 Pack Materials-Page 2 21-Sep-2010 Width (mm) Height (mm) 346.0 346.0 41.0 ...

  • Page 106

    PAG (S-PQFP-G64) 0, 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 107

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...