The TPS54040 device is a 42-V 0

TPS54040-Q1

Manufacturer Part NumberTPS54040-Q1
DescriptionThe TPS54040 device is a 42-V 0
ManufacturerTexas Instruments
TPS54040-Q1 datasheet
 


Specifications of TPS54040-Q1

Iout(max)(a)0.5Vin(min)(v)3.5
Vin(max)(v)42Vout(min)(v)0.8
Vout(max)(v)39Iq(typ)(ma)0.116
Switching Frequency(max)(khz)2500Switch Current Limit(typ)(a)0.6
TopologyBuck,Inverting Buck-BoostOperating Temperature Range(c)-40 to 125
Pin/package10MSOP-PowerPAD, 10SONDuty Cycle(max)(%)95
Regulated Outputs(#)1  
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Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. See
Figure 63
for a PCB layout example. The GND pin should be tied directly to the power pad under the
IC and the power pad.
The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated
load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise
so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The
additional external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
Topside
Ground
Route Boot Capacitor
Area
Trace on another layer to
provide wide path for
topside ground
Input
Bypass
Capacitor
Vin
UVLO
Adjust
Resistors
Slow Start
Capacitor
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of
does not include test points or connectors.
Copyright © 2010–2011, Texas Instruments Incorporated
Vout
Output
Capacitor
BOOT
PH
VIN
GND
EN
COMP
SS/TR
VSENSE
PWRGD
RT/CLK
Frequency
Set Resistor
Figure 63. PCB Layout Example
TPS54040-Q1
SLVSA26C – JANUARY 2010 – REVISED AUGUST 2011
Output
Inductor
Catch
Diode
Compensation
Resistor
Network
Divider
Thermal VIA
Signal VIA
2
Figure 50
is 0.55 in
. This area
39