As a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components

TPS54073

Manufacturer Part NumberTPS54073
DescriptionAs a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components
ManufacturerTexas Instruments
TPS54073 datasheet
 


Specifications of TPS54073

Iout(max)(a)14Vin(min)(v)2.2
Vin(max)(v)4Vout(min)(v)0.9
Vout(max)(v)2.5Iq(typ)(ma)13
Switching Frequency(max)(khz)700Switch Current Limit(typ)(a)14.5
TopologyBuckOperating Temperature Range(c)-40 to 85
Pin/package28HTSSOPDuty Cycle(max)(%)90
Regulated Outputs(#)1  
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............................................................................................................................................................................................
phase margin at crossover must be greater than 45
degrees. The general procedure outlined here
produces results consistent with these requirements
without going into great detail about the theory of loop
compensation.
First, calculate the output filter LC corner frequency
using
Equation
11:
1
+
LC
2p L
C
OUT
OUT
For the design example, f
= 5.906 kHz.
LC
The closed-loop crossover frequency should be
chosen to be greater than f
and less than one-fifth
LC
of the switching frequency. Also, the crossover
frequency should not exceed 100 kHz, as the error
amplifier may not provide the desired gain. For this
design, a crossover frequency of 40 kHz was chosen.
This value is chosen for comparatively wide loop
bandwidth while still allowing for adequate phase
boost to insure stability.
Next, calculate the R2 resistor value for the output
voltage of 1.5 V using
Equation
12:
R1
0.891
R2 +
V
* 0.891
OUT
For any TPS54073 design, start with an R1 value of
10 kΩ. R2 is 14.7 kΩ.
Now, the values for the compensation components
that set the poles and zeros of the compensation
network can be calculated. Assuming that R1 >> than
R5 and C6 >> C7, the pole and zero locations are
given by
Equation 13
through
Equation
1
+
Z1
2pR3C6
1
+
Z2
2pR1C8
1
+
P1
2pR5C8
1
+
P2
2pR3C7
Additionally, there is a pole at the origin, which has
unity gain at a frequency:
1
+
INT
2pR1C6
This pole is used to set the overall gain of the
compensated error amplifier and determines the
closed-loop crossover frequency. Because R1 is
given as 10 kΩ and the nominal crossover frequency
is selected as 40 kHz, the desired f
calculated from
Equation
18:
Copyright © 2005, Texas Instruments Incorporated
f
´
CO
f
=
INT
V
IN(NOM)
For this design, one zero is placed at f
other at one fourth f
f
CO
f
=
INT
V
IN(NOM)
(11)
It is important to note that these equations are only
valid for the pole and zero locations as specified
The value for C6 is given by
1
C6 +
2pR1
INT
The first zero, f
filter LC corner frequency; so, R3 can be calculated
from:
1
R3 +
pC6
LC
The second zero, f
corner frequency; so, C8 can be calculated from:
(12)
1
C8 +
2pR1
LC
The first pole, f
filter ESR zero frequency. This frequency is given by:
+
ESR0
2pR
20:
where R
is the equivalent series resistance of the
ESR
output capacitor.
(13)
In this case, the ESR zero frequency is 48.2 kHz, and
R5 can be calculated from:
(14)
1
R5 +
2pC8
ESR
(15)
The final pole is placed at a frequency above the
(16)
closed-loop crossover frequency high enough to not
cause the phase to decrease too much at the
crossover frequency while still providing enough
attenuation so that there is little or no gain at the
switching frequency. The f
(17)
circuit is set to 150 kHz and the last compensation
component value C7 can be derived:
C7 =
2 R3 x 150000
p
Note that capacitors are only available in a limited
can be
INT
range of standard values, so the nearest standard
value has been chosen for each capacitor. The
measured closed-loop response for this design is
shown in
Figure
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TPS54073
TPS54073
SLVS547 – FEBRUARY 2005
f
f
´
Z1
Z2
2
f
´
LC
and the
LC
, so
Equation 18
simplifies to:
LC
4
´
Equation
20:
is located at one-half the output
Z1
is located at the output filter LC
Z2
is located to coincide with output
P1
1
C
ESR
OUT
pole location for this
P2
1
5.
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(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
13