As a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components

TPS54073

Manufacturer Part NumberTPS54073
DescriptionAs a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components
ManufacturerTexas Instruments
TPS54073 datasheet
 


Specifications of TPS54073

Iout(max)(a)14Vin(min)(v)2.2
Vin(max)(v)4Vout(min)(v)0.9
Vout(max)(v)2.5Iq(typ)(ma)13
Switching Frequency(max)(khz)700Switch Current Limit(typ)(a)14.5
TopologyBuckOperating Temperature Range(c)-40 to 85
Pin/package28HTSSOPDuty Cycle(max)(%)90
Regulated Outputs(#)1  
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OPERATING WITH SEPARATE PVIN
The TPS54073 is designed to operate with the power stage (high-side and low-side MOSFETs) and the PVIN
input connected to a separate power source from VIN. The primary intended application has VIN connected to a
3.3-V bus and PVIN connected to a 2.5-V bus. The TPS54073 cannot be damaged by any sequencing of these
voltages. However, the UVLO (see detailed description section) is referenced to the VIN input. Some conditions
may cause undesirable operation.
If PVIN is absent when the VIN input is high, the slow-start is released, and the PWM circuit goes to maximum
duty factor. When the PVIN input ramps up, the output of the TPS54073 follows the PVIN input until enough
voltage is present to regulate to the proper output value.
If the PVIN input is controlled via a fast bus switch, it results in a hard-start condition
and may damage the load (i.e., whatever is connected to the regulated output of the
TPS54073). If a power-good signal is not available from the 2.5-V power supply, one
can be generated using a comparator and hold the SS/ENA pin low until the 2.5-V
bus power is good. An example of this is shown in
used to prevent the TPS54073 output from following the PVIN input while the PVIN
power supply is ramping up.
DISABLED SINKING DURING START-UP (DSDS)
The DSDS feature enables minimal voltage drooping of output precharge capacitors at start-up. The TPS54073
is designed to disable the low-side MOSFET to prevent sinking current from a precharge output capacitor during
start-up. Once the high-side MOSFET has been turned on to the maximum duty cycle limit, the low-side
MOSFET is allowed to switch. Once the maximum duty cycle condition is met, the converter functions as a
sourcing converter until the SS/ENA is pulled low.
Figure 27. Undervoltage Lockout Circuit for PVIN Using Open-Collector or Open-Drain Comparator
PVIN and VIN can be tied together for 3.3-V bus operation.
MAXIMUM OUTPUT VOLTAGE
The maximum attainable output voltage is limited by the minimum voltage at the PVIN pin. Nominal maximum
duty cycle is limited to 90% in the TPS54073; so, maximum output voltage is:
V
+ PVIN
0.9
O(max)
(min)
Care must be taken while operating when nominal conditions cause duty cycles near 90%. Load transients can
require momentary increases in duty cycle. If the required duty cycle exceeds 90%, the output may fall out of
regulation.
Copyright © 2005, Texas Instruments Incorporated
DETAILED DESCRIPTION
NOTE:
Figure
27. This circuit can also be
100 k
VIN
10 k
PVIN
+
SS/ENA
VBIAS
10 k
1/2 LM293
27.4 k
Product Folder Link(s):
TPS54073
TPS54073
SLVS547 – FEBRUARY 2005
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