As a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components

TPS54073

Manufacturer Part NumberTPS54073
DescriptionAs a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components
ManufacturerTexas Instruments
TPS54073 datasheet
 


Specifications of TPS54073

Iout(max)(a)14Vin(min)(v)2.2
Vin(max)(v)4Vout(min)(v)0.9
Vout(max)(v)2.5Iq(typ)(ma)13
Switching Frequency(max)(khz)700Switch Current Limit(typ)(a)14.5
TopologyBuckOperating Temperature Range(c)-40 to 85
Pin/package28HTSSOPDuty Cycle(max)(%)90
Regulated Outputs(#)1  
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TPS54073
SLVS547 – FEBRUARY 2005
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GROUNDING AND PowerPAD LAYOUT
The TPS54073 has two internal grounds (analog and power). Inside the TPS54073, the analog ground ties to all
of the noise-sensitive signals, whereas the power ground ties to the noisier power signals. The PowerPAD must
be tied directly to AGND. Noise injected between the two grounds can degrade the performance of the
TPS54073, particularly at higher output currents. However, ground noise on an analog ground plane can also
cause problems with some of the control and bias signals. For these reasons, separate analog and power ground
planes are recommended. These two planes must tie together directly at the IC to reduce noise between the two
grounds. The only components that must tie directly to the power ground plane are the input capacitor, the output
capacitor, the input voltage de-coupling capacitor, and the PGND pins of the TPS54073.
UNDERVOLTAGE LOCKOUT (UVLO)
The TPS54073 incorporates an undervoltage-lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5- s rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN. UVLO is with respect to VIN and not PVIN, see the Application Information section.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions. First, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5- s falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and AGND.
Adding a capacitor to the SS/ENA pin has two effects on start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The start-up delay is approximately:
1.2 V
t
+ C
d
(SS)
5 mA
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7 V
t
+ C
(SS)
(SS)
5 mA
The actual slow-start time is likely to be less than the above approximation due to the brief ramp-up at the
internal rate.
VBIAS REGULATOR (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high-quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. The bypass capacitor must be placed close to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.7 V,
and external loads on VBIAS with ac or digital-switching noise may degrade performance. The VBIAS pin may be
useful as a reference voltage for external circuits. VBIAS is derived from the VIN pin; see the functional block
diagram of this data sheet.
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