As a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components

TPS54073

Manufacturer Part NumberTPS54073
DescriptionAs a member of the SWIFT™ family of dc/dc regulators, the TPS54073 low-input voltage high-output current synchronous buck PWM converter integrates all required active components
ManufacturerTexas Instruments
TPS54073 datasheet
 


Specifications of TPS54073

Iout(max)(a)14Vin(min)(v)2.2
Vin(max)(v)4Vout(min)(v)0.9
Vout(max)(v)2.5Iq(typ)(ma)13
Switching Frequency(max)(khz)700Switch Current Limit(typ)(a)14.5
TopologyBuckOperating Temperature Range(c)-40 to 85
Pin/package28HTSSOPDuty Cycle(max)(%)90
Regulated Outputs(#)1  
1
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............................................................................................................................................................................................
Connect the output filter capacitor(s) between the
VOUT trace and PGND. It is important to keep the
loop formed by the PH pins, Lout, Cout, and PGND
as small as is practical. Place the compensation
components from the VOUT trace to the VSENSE
and COMP pins. Do not place these components too
close to the PH trace. Due to the size of the IC
package and the device pinout, they must be routed
close, but maintain as much separation as possible
while keeping the layout compact. Connect the bias
capacitor from the VBIAS pin to analog ground using
the isolated analog ground trace. If a slow-start
capacitor or RT resistor is used, or if the SYNC pin is
used to select 350-kHz operating frequency, connect
them to this trace.
Optional
prebias
diodes
should
between the output voltage trace and the prebias
source. The source is VIN, PVIN, or some other
voltage rail. This is dependent on the user's
application circuit. In some cases, the diodes are not
required if the prebias voltage is caused by an
external load circuit leakage path.
8 PL
4 PL
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
0.3820
0.3478
Minimum Recommended Top
Side Analog Ground Area
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
Copyright © 2005, Texas Instruments Incorporated
For operation at full rated load current, the analog
ground
heat-dissipating area. A 3-inch by 3-inch plane of
1-ounce
mandatory, depending on ambient temperature and
airflow. Most applications have larger areas of
internal ground plane available, and the PowerPAD
must be connected to the largest area available.
Additional areas on the top or bottom layers also help
dissipate heat, and any area available must be used
when 6-A or greater operation is desired. Connection
from the exposed area of the PowerPAD to the
analog ground plane layer must be made using
0.013-inch diameter vias to avoid solder wicking
through the vias.
be
connected
Eight vias must be in the PowerPAD area with four
additional vias located under the device package. The
size of the vias under the package, but not in the
exposed thermal pad area, can be increased to
0.018.
recommended that enhance thermal performance
must be included in areas not under the device
package.
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
PowerPAD Area 4 x 0.018 Diameter Under Device as Shown.
Ø 0.0130
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Ø 0.0180
Area Is Extended.
0.0150
0.06
0.0339
0.0650
0.0500
0.0500
0.0500
0.0256
0.0650
0.0339
0.1700
0.1340
0.0630
0.0400
Product Folder Link(s):
TPS54073
TPS54073
SLVS547 – FEBRUARY 2005
plane
must
provide
an
copper
is
recommended,
though
Additional
vias
beyond
the
0.2090
Minimum Recommended Exposed
Copper Area for PowerPAD. 5mm
Stencils May Require 10 Percent
Larger Area
Submit Documentation Feedback
adequate
not
twelve
9