The TPS54383 and TPS54386 are dual output, non-synchronous buck converters capable of supporting 3-A output applications that operate from a 4

TPS54383

Manufacturer Part NumberTPS54383
DescriptionThe TPS54383 and TPS54386 are dual output, non-synchronous buck converters capable of supporting 3-A output applications that operate from a 4
ManufacturerTexas Instruments
TPS54383 datasheet
 


Specifications of TPS54383

Iout(max)(a)3Iout2(max)(a)3
Vin(min)(v)4.5Vin(max)(v)28
Vout(min)(v)0.8Vout(max)(v)25.2
Iq(typ)(ma)1.8Switching Frequency(typ)(khz)300
Switch Current Limit(typ)(a)4.5TopologyBuck
Operating Temperature Range(c)-40 to 125Pin/package14HTSSOP
Duty Cycle(max)(%)90Vout2(min)(v)0.8
Vout2(max)(v)25.2Regulated Outputs(#)2
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3-A DUAL NON-SYNCHRONOUS CONVERTER WITH INTEGRATED HIGH-SIDE MOSFET
FEATURES
1
4.5-V to 28-V Input Range
23
Output Voltage Range 0.8 V to 90% of Input
Voltage
Output Current Up to 3 A
Two Fixed Switching Frequency Versions:
– TPS54383: 300 kHz
– TPS54386: 600 kHz
Three Selectable Levels of Overcurrent
Protection (Output 2)
0.8-V 1.5% Voltage Reference
2.1-ms Internal Soft Start
Dual PWM Outputs 180 Out-of-Phase
Ratiometric or Sequential Startup Modes
Selectable by a Single Pin
85-mΩ Internal High-Side MOSFETs
Current Mode Control
Internal Compensation (See Page 16)
Pulse-by-Pulse Overcurrent Protection
Thermal Shutdown Protection at +148 C
14-Pin PowerPAD™ HTSSOP package
APPLICATIONS
Set Top Box
Digital TV
Power for DSP
Consumer Electronics
OUTPUT1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007
CONTENTS
Device Ratings
Electrical Characteristics
Device Information
Application Information
Design Examples
Additional References
DESCRIPTION
The TPS54383 and TPS54386 are dual output,
non-synchronous
buck
supporting 3-A output applications that operate from a
4.5-V to 28-V input supply voltage, and require output
voltages between 0.8 V and 90% of the input voltage.
With an internally-determined operating frequency,
soft start time, and control loop compensation, these
converters provide many features with a minimum of
external
components.
protection is set at 4.5 A, while Channel 2 overcurrent
protection level is selected by connecting a pin to
ground, to BP, or left floating. The setting levels are
used to allow for scaling of external components for
applications that do not need the full load capability of
both outputs.
The outputs may be enabled independently, or may
be configured to allow either ratiometric or sequential
startup sequencing. Additionally, the two outputs may
be powered from different sources.
V
IN
TPS54383
1
PVDD1
PVDD2
14
2
BOOT1
BOOT2
13
3
SW1
SW2
12
4
GND
BP
11
5
EN1
SEQ
10
6
EN2
ILIM2
9
7
FB1
FB2
8
GND
Copyright © 2007, Texas Instruments Incorporated
TPS54383, , TPS54386
2
3
9
12
32
44
converters
capable
of
Channel
1
overcurrent
OUTPUT2
UDG-07123

TPS54383 Summary of contents

  • Page 1

    ... Electrical Characteristics Device Information Application Information Design Examples Additional References DESCRIPTION The TPS54383 and TPS54386 are dual output, non-synchronous buck supporting 3-A output applications that operate from a 4.5-V to 28-V input supply voltage, and require output voltages between 0.8 V and 90% of the input voltage. With an internally-determined operating frequency, ...

  • Page 2

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PART NUMBER OPERATING FREQUENCY (kHz) ...

  • Page 3

    ... C < T < +125 ILIM2 (floating) ILIM2 V = GND ILIM2 Measured at feedback pin. Input UVLO and Startup section. Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 MIN TYP MAX UNIT 4 150 1.8 3 3.8 4.1 4.4 ...

  • Page 4

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) –40 C ≤ T ≤ +125 unless otherwise noted. J PVDD1 PVDD2 PARAMETER BOOTSTRAP R BOOT1 Bootstrap switch resistance R BOOT2 OUTPUT STAGE (Channel 1 and Channel 2) (3) R MOSFET on resistance plus bond wire resistance ...

  • Page 5

    ... C 1.25 EN(Off) 1.23 1.21 EN(On) 1.19 1.17 1.15 75 100 125 -50 -25 - ° C Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 SHUTDOWN CURRENT vs JUNCTION TEMPERATURE PVDDx PVDDx V = 4.5 V PVDDx 100 125 T - Junction Temperature - ° ...

  • Page 6

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) SOFT START TIME vs JUNCTION TEMPERATURE 3 5. 3.0 2.5 2.0 1.5 -50 - Junction Temperature J Figure 5. SWITCHING FREQUENCY (600 kHz) vs JUNCTION TEMPERATURE 680 660 640 620 600 580 -50 - Junction Temperature ...

  • Page 7

    ... OVERCURRENT LIMIT (CH2 LOW LEVEL) 1 PVDDx 1.6 1.4 V PVDDx = 5 V 1.2 75 100 125 -50 - ° Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 vs JUNCTION TEMPERATURE PVDD PVDD 100 125 T - Junction Temperature - ° Figure 10 ...

  • Page 8

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS (continued) SWITCHING NODE LEAKAGE CURRENT vs JUNCTION TEMPERATURE -50 - Junction Temperature - °C J Figure 13. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 8 Submit Documentation Feedback MINUMUM CONTROLLABLE PULSE WIDTH 400 350 300 250 200 ...

  • Page 9

    ... SEQ EN2 6 9 ILIM2 FB1 7 8 FB2 section for further information. section for further information. Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Feedback Feedback Table 2, Current Limit Threshold Adjustment for Submit Documentation Feedback 9 ...

  • Page 10

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. This pin configures the output startup mode. If the SEQ pin is connected to BP, then when Output 2 is enabled, Output 1 is allowed to start after Output 2 has reached regulation; that is, sequential startup where Output 1 is slave to Output 2 ...

  • Page 11

    ... Overcurrent Comp R COMP f(I ) f(I ) SLOPE2 MAX2 C COMP 5.25-V PVDD2 Regulator 0.8 V REF References I (Set to one of three limits) MAX2 Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 2 BOOT1 1 PVDD1 SW1 BP Weak CLK1 Pull-Down Anti-Cross MOSFET Conduction f(I ) ...

  • Page 12

    ... SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 FUNCTIONAL DESCRIPTION The TPS54383 and TPS54386 are dual output, non-synchronous converters. Each PWM channel contains an internally-compensated error amplifier, current mode pulse width modulator (PWM), switch MOSFET, enable, and fault protection circuitry. Common to the two channels are the internal voltage regulator, voltage reference, clock oscillator, and output voltage sequencing functions ...

  • Page 13

    ... Copyright © 2007, Texas Instruments Incorporated farads PVDD2 6 mA PVDDx + ENx V OUTx Figure 17. Startup Delay with R-C on Enable DESIGN HINT section.) Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Equation Output Voltage Sequencing 1.2-V Threshold DELAY DELAY SS T ...

  • Page 14

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Output Voltage Sequencing The TPS5438x allows single-pin programming of output voltage startup sequencing. During power-on, the state of the SEQ pin is detected. Based on whether the pin is tied to BP, to GND, or left floating, the outputs behave ...

  • Page 15

    ... Enable and Timed Turn On of the 5-V VOUT1 (2 V/div) 3.3-V VOUT2 (2 V/div Time - 1 ms/div Figure 20. SEQ Pin Floating NOTE: Once the filter and compensation DESIGN HINT Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Outputs. Feedback Loop Submit Documentation Feedback 15 ...

  • Page 16

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 to support the desired regulation voltage by the time Soft Start has completed, then the output UV circuit may trip and cause a hiccup in the output voltage. In this case, use a timed delay startup from the ENx pin to delay the startup of the output until the PVDDx voltage has the capability of supporting the desired regulation voltage ...

  • Page 17

    ... COMP SLOPE x2 I SLOPE + I COMP 11.5 kW the next section) of gain and phase are used along with Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 -type error amplifier M amplifier output to M Figure SW Node PWM to Switch Offset f(I ) ...

  • Page 18

    ... M 100 Figure 25. TPS54383 at 400-mApp Ripple Current Product Folder Link(s): TPS54383 TPS54386 www.ti.com VOUT Filter GAIN AND PHASE vs FREQUENCY 270 225 180 135 -45 - 100 ...

  • Page 19

    ... GAIN AND PHASE vs FREQUENCY 100 Duty Cycle % Gain Phase -20 100 Frequency -Hz Figure 26. TPS54383 at 600-mApp Ripple Current GAIN AND PHASE vs FREQUENCY 100 Duty Cycle % Gain Phase -20 100 Frequency -Hz Figure 28 ...

  • Page 20

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 OUTmax CLx REF V REF Minimum Output Capacitance Ensure the value of capacitance selected for closed loop stability is compatible with the requirements of Start. Modifying The Feedback Loop Within the limits of the internal compensation, there is flexibility in the selection of the inductor and output capacitor values ...

  • Page 21

    ... This frequency should be placed ZERO(desired) between 20 kHz and 60 kHz to ensure good loop stability. Copyright © 2007, Texas Instruments Incorporated Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Submit Documentation Feedback (4) 21 ...

  • Page 22

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 The value of the capacitor is calculated ´ ´ ESR(zero) where equivalent impedance created by the parallel combination of the voltage setting divider resistors (R1 EQ and R2) in series with R3. ...

  • Page 23

    ... GAIN AND PHASE vs FREQUENCY Phase Gain 100 k f Frequency Figure 31. Example Loop Result Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Ripple Current (P-P) Figure 28, find the 30% duty cycle W 180 135 -45 -90 -135 -180 ...

  • Page 24

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Bootstrap for the N-Channel MOSFET A bootstrap circuit provides a voltage source higher than the input voltage and of sufficient energy to fully enhance the switching MOSFET each switching cycle. The PWM duty cycle is limited to a maximum of 90%, allowing an external bootstrap capacitor to charge through an internal synchronous switch (between BP and BOOTx) during every cycle ...

  • Page 25

    ... OUT DESIGN HINT Feedback Loop and Inductor-Capacitor (L-C) sections. DESIGN HINT DESIGN HINT DESIGN HINT Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Skipping OUT Inductor Current Figure 33. Skipping Submit Documentation Feedback ...

  • Page 26

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Output Overload Protection In the event of an overcurrent during soft start on either output (such as starting into an output short), pulse-by-pulse current limiting and PWM frequency division are in effect for that output until the internal soft start timer ends ...

  • Page 27

    ... BOOT1 BOOT2 13 3 SW1 SW2 12 4 GND EN1 SEQ 10 6 EN2 ILIM2 9 7 FB1 FB2 8 Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 section.) Figure 35. This configuration may be OUTPUT2 UDG-07015 Submit Documentation Feedback 27 ...

  • Page 28

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 PVDD2 Output2 PVDD1 Output1 Figure 35. Waveforms Resulting from Cascading PVDD1 from Output 2 In this configuration, the following conditions must be maintained: 1. Output 2 must voltage high enough to maintain regulation of Output 1 under all load conditions. ...

  • Page 29

    ... D(cond)output2 D(SW )output2 table), plus the thermal impedance from the thermal pad to ambient. The PCB Layout Guidelines, Additional References Equation 20 Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 V Iq ´ IN section. Submit Documentation Feedback (16) (17) ...

  • Page 30

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 PowerPAD Package The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit board must have an area of solder-tinned-copper underneath the package ...

  • Page 31

    ... Figure 37. Top Layer Copper Layout and Component Placement Copyright © 2007, Texas Instruments Incorporated L2 C14 R8 C17 D2 C11 R9 C16 C10 Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 VOUT2 GND GND VOUT1 Submit Documentation Feedback 31 ...

  • Page 32

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 32 Submit Documentation Feedback Figure 38. Bottom Layer Copper Layout Product Folder Link(s): TPS54383 TPS54386 www.ti.com Copyright © 2007, Texas Instruments Incorporated ...

  • Page 33

    ... Example 1: Detailed Design of a 12-V to 5-V and 3.3-V Converter The following example illustrates a design process and component selection for a 12-V to 5-V and 3.3-V dual non-synchronous buck regulator using the TPS54383 converter. Design Example List of Materials and Definition of Symbols is found at the end of this section. PARAMETER ...

  • Page 34

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Design Procedure Duty Cycle Estimation The first step is to estimate the duty cycle of each switching FET OUT FD D » max IN(min OUT FD D » min IN(max) FD Using an assumed forward drop of 0.5 V for a schottky rectifier diode, the Channel 1 duty cycle is approximately 40 ...

  • Page 35

    ... For this design, the full load power dissipation is estimated to be 480 mW in D1, and 580 mW in D2. Output Capacitor Selection The TPS54383's internal compensation limits the selection of the output capacitors. From compensation has a double zero resonance at about 3 kHz. The output capacitor is selected ...

  • Page 36

    ... ESR(zero 10.9 nF (10 nF selected) C15 = 7.22 nF (6800 pF selected) Input Capacitor Selection The TPS54383 datasheet recommends a minimum 10- F ceramic input capacitor on each PVDD pin. These capacitor must be capable of handling the RMS ripple current of the converter. The RMS current in the input capacitors is estimated by Equation ...

  • Page 37

    ... The SEQ pin is left floating, leaving the enable pins to function independently. If the enable pins are tied together, the two supplies start-up ratiometrically. Alternatively, SEQ could be connected GND to provide sequential start-up. Power Dissipation The power dissipation in the TPS54383 is composed of FET conduction losses, switching losses and internal regulator losses. The RMS FET current is found using æ æ ...

  • Page 38

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 The total power dissipation is P =0.198+0.136+0.017+0.017+.066 = 434 mW. DISS Design Example Test Results The following results are from the TPS54383-001 EVM. 100 ...

  • Page 39

    ... IN 9.6 12.0 0.996 13.2 0.995 2.0 2.5 3.0 0 Figure 44. 3.3-V Output Voltage vs. Load Current Gain Phase 5 100 Frequency -Hz Figure 45. Example 1 Loop Response Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 3.3 V OUT (V) IN 9.6 12.0 13.2 0.5 1.0 1.5 2 ...

  • Page 40

    ... R6, R10 10 Ω Resistor, Chip, 1/16W 698 Ω Resistor, Chip, 1/16W 3.83 kΩ Resistor, Chip, 1/16W 6.34 kΩ Resistor, Chip, 1/16W, 1% TPS54383 DC-DC Switching Converter FET 40 Submit Documentation Feedback DESCRIPTION SIZE E-can 1210 0805 0603 0603 F-can 0805 0603 ...

  • Page 41

    ... Peak to Peak ripple voltage due to ideal capacitor (ESR = 0 ) RIPPLE(cap) V Maximum allowable peak to peak output ripple voltage RIPPLE(tot) Copyright © 2007, Texas Instruments Incorporated Table 4. Definition of Symbols Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Submit Documentation Feedback 41 ...

  • Page 42

    ... For a higher input voltage, both a snubber and bootstrap resistors are added to reduce ringing on the switch node and schottky diode is selected. A higher resistance feedback network is chosen for the 12 V output to reduce the feedback current. + Figure 46. 24-V to 12-V and 24-V to 5-V Using the TPS54383 ...

  • Page 43

    ... Copyright © 2007, Texas Instruments Incorporated OUT OUT 0.5 1.0 1.5 2 Load Current - A OUT Figure 49. Efficiency vs. Load Current Product Folder Link(s): TPS54383 TPS54386 TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 = 24 V (V) OUT 5 12 2.5 3.0 Submit Documentation Feedback 43 ...

  • Page 44

    ... TPS54383, , TPS54386 SLUS774B – AUGUST 2007 – REVISED OCTOBER 2007 Example 3: 5-V to 3.3V and 5-V to 1.2 V For a low input voltage application, the TPS54386 is selected for reduced size and all ceramic output capacitors are used. 22- F input capacitors are selected to reduce input ripple and lead capacitors are placed in the feedback to boost phase margin ...

  • Page 45

    ... Related Devices The following parts have characteristics similar to the TPS54383/6 and may be of interest. Table 5. Devices Related to the TPS54383 and TPS54386 TI LITERATURE DEVICE NUMBER SLUS642 TPS40222 TPS54283 / SLUS749 TPS54286 References These references, design tools and links to additional references, including design software, may be found at http:www ...

  • Page 46

    ... PACKAGING INFORMATION (1) Orderable Device Status TPS54383PWP ACTIVE TPS54383PWPG4 ACTIVE TPS54383PWPR ACTIVE TPS54383PWPRG4 ACTIVE TPS54386PWP ACTIVE TPS54386PWPG4 ACTIVE TPS54386PWPR ACTIVE TPS54386PWPRG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...

  • Page 47

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TPS54383PWPR HTSSOP PWP TPS54386PWPR HTSSOP PWP PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 14 2000 330.0 12.4 6.9 14 2000 330.0 12.4 6.9 Pack Materials-Page 1 25-Sep-2009 Pin1 ...

  • Page 48

    ... Device Package Type TPS54383PWPR HTSSOP TPS54386PWPR HTSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PWP 14 2000 PWP 14 2000 Pack Materials-Page 2 25-Sep-2009 Width (mm) Height (mm) 346.0 346.0 29.0 346.0 346.0 29.0 ...

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    ... PACKAGING INFORMATION Orderable Device (1) Package Type Package Status TPS54383PWP ACTIVE HTSSOP TPS54383PWPG4 ACTIVE HTSSOP TPS54383PWPR ACTIVE HTSSOP TPS54383PWPRG4 ACTIVE HTSSOP TPS54386PWP ACTIVE HTSSOP TPS54386PWPG4 ACTIVE HTSSOP TPS54386PWPR ACTIVE HTSSOP TPS54386PWPRG4 ACTIVE HTSSOP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs ...

  • Page 53

    Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or ...

  • Page 54

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TPS54383PWPR HTSSOP PWP TPS54386PWPR HTSSOP PWP PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 14 2000 330.0 12.4 6.9 14 2000 330.0 12.4 6.9 Pack Materials-Page 1 25-Sep-2009 Pin1 ...

  • Page 55

    ... Device Package Type TPS54383PWPR HTSSOP TPS54386PWPR HTSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PWP 14 2000 PWP 14 2000 Pack Materials-Page 2 25-Sep-2009 Width (mm) Height (mm) 346.0 346.0 29.0 346.0 346.0 29.0 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...