The PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages

PCM1681

Manufacturer Part NumberPCM1681
DescriptionThe PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages
ManufacturerTexas Instruments
PCM1681 datasheet
 


Specifications of PCM1681

# Dacs8# Inputs / # Outputs0 / 8
ArchitectureCurrent Segment DACResolution(bits)24
Sampling Rate(max)(khz)200Control InterfaceSPI, I2C,H/W
Digital Audio InterfaceL,R,I2S,TDM,DSPThd+n(typ)(%)0.002
Dac Snr(typ)(db)105Power Consumption(typ)(mw)386
Operating Temperature Range(c)-40 to 85Analog Voltage Av/dd(min)(v)4.5
Analog Voltage Av/dd(max)(v)5.5Pin/package28HTSSOP
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OVERSAMPLING RATE CONTROL
The PCM1681 and PCM1681-Q1 automatically control the oversampling rate of the ΔΣ DACs according to
system clock frequency and oversampling mode. Oversampling mode, narrow or wide, can be selected by the
MSEL pin in H/W control mode and the OVER bit of control register 12 in S/W control mode. The oversampling
rate is set to 64× oversampling with a 1152 f
f
system clock, and 16× oversampling with a 192 f
S
oversampling with a 1152 f
, 768 f
S
S
and 32× oversampling with a 192 f
S
kHz at SCK = 128 f
or 192 f
, f
≤ 48 kHz at SCK = 256 f
S
S
S
1152 f
.
S
OVERSAMPLING MODE
SCK = 128 f
Narrow mode
Wide mode
ZERO FLAG
The PCM1681 and PCM1681-Q1 have two zero-flag pins, ZR1 (pin 1) and ZR2 (pin 28), which are assigned to
the combinations A through D as shown in
combination bits, AZRO[1:0], located in control register 13 of the PCM1681 and PCM1681-Q1. If the input data of
the L-channel and/or R-channel of all assigned channels remains at a logic-0 level for 1024 sampling periods
(LRCK clock periods), ZR1 and ZR2 are set to logic-1 states, or high level. If the input data of any of the
assigned channels contains a logic-1 level, ZR1 and ZR2 are set to logic-0 states or low level immediately.
The active polarity of a zero-flag output can be inverted by setting the ZREV bit of control register 10 to 1. The
reset default is ZREV = 0, active-high for zero detection.
In parallel hardware control mode, ZR1 is not applicable due to the reassignment of ZR1 as the FMT0 control
pin, and the zero-flag output combination is fixed as all 8 channel (DATA1-DATA4) data zero on the ZR2 pin.
Table 4. Zero-Flag Output Combinations
ZERO-FLAG COMBINATION
A
B
C
D
MODE CONTROL
The PCM1681 and PCM1681-Q1 support three types of interface mode control with three types of oversampling
configuration, according to the input state of MSEL (pin 14) as listed in
pull-up and pull-down resistors are 220 kΩ ± 5%.
MSEL
Tied with DGND
Pull-down resistor to DGND
Pull-up resistor to V
DD
Tied with V
DD
Copyright © 2008, Texas Instruments Incorporated
, 768 f
, 512 f
system clock, 32× oversampling with a 384 f
S
S
S
, 128 f
system clock in default, narrow mode, and 128×
S
S
, 512 f
system clock, 64× oversampling with a 384 f
S
, 128 f
system clock in wide mode. Wide mode is recommended for f
S
or 384 f
, and f
S
S
Table 3. Oversampling Rate Control
OVERSAMPLING RATE
or 192 f
SCK = 256 f
S
S
S
16×
32×
32×
64×
Table
4. Zero-flag combinations are selected using the zero-flag
ZR1/ZR1/FMT0 (PIN 1)
DATA1 L-ch
DATA1-4
DATA4
DATA1
Table 5. Interface Mode Control
INTERFACE MODE CONTROL
2
2-Wire (I
C) serial control, selectable oversampling configuration
4-Wire parallel H/W control, narrow mode oversampling configuration
4-Wire parallel H/W control, wide mode oversampling configuration
3-Wire (SPI) serial control, selectable oversampling configuration
Product Folder Link(s):
PCM1681 PCM1681-Q1
PCM1681
PCM1681-Q1
SLES211B – FEBRUARY 2008 – REVISED JUNE 2008
S
, 256 f
system clock,
S
S
S
≤ 24 kHz at SCK = 512 f
, 768 f
S
S
or 384 f
SCK = 512 f
, 768 f
, or 1152 f
S
S
S
64×
128×
ZR2 (PIN 28)
DATA1 R-ch
DATA1-4
DATA1-3
DATA2-4
Table
5. The required values of the
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, 256
≤ 96
, or
S
S
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