The PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages

PCM1681

Manufacturer Part NumberPCM1681
DescriptionThe PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages
ManufacturerTexas Instruments
PCM1681 datasheet
 


Specifications of PCM1681

# Dacs8# Inputs / # Outputs0 / 8
ArchitectureCurrent Segment DACResolution(bits)24
Sampling Rate(max)(khz)200Control InterfaceSPI, I2C,H/W
Digital Audio InterfaceL,R,I2S,TDM,DSPThd+n(typ)(%)0.002
Dac Snr(typ)(db)105Power Consumption(typ)(mw)386
Operating Temperature Range(c)-40 to 85Analog Voltage Av/dd(min)(v)4.5
Analog Voltage Av/dd(max)(v)5.5Pin/package28HTSSOP
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2
I
C INTERFACE
The PCM1681 and PCM1681-Q1 support the I
mode as a slave device. This protocol is explained in the I
do not support a board-to-board interface. The I
DGND and after power-on reset completion.
SLAVE ADDRESS
MSB
1
0
0
The PCM1681 and PCM1681-Q1 have seven bits for the respective slave address. The first six bits (MSBs) of
the slave address are factory preset to 1001 10. The next bit of the address byte is the device select bit, which
can be user-defined using the ADR terminal. A maximum of two PCM1681s or PCM1681-Q1s can be connected
on the same bus at one time. Each PCM1681 or PCM1681-Q1 responds when it receives its own slave address.
PACKET PROTOCOL
A master device must control packet protocol, which consists of a start condition, slave address, read/write bit,
data if writing or acknowledge if reading, and stop condition. The PCM1681 and PCM1681-Q1 support only slave
receivers and slave transmitters. The details about DATA for write and read operation are described in the
following sections.
SDA
SCL
St
1−7
Slave Address
R/W
R/W:
Start
ACK: Acknowledgement of a Byte if 0
Condition
DATA: 8 Bits (Byte), the details are described in write and read operation
NACK: Not Acknowledgement if 1
Write Operation
Transmitter
M
M
Data Type
St
Slave Address
Read Operation
Transmitter
M
M
Data Type
St
Slave Address
M: Master Device S: Slave Device St: Start Condition
Sp: Stop Condition W: Write R: Read
Copyright © 2008, Texas Instruments Incorporated
2
C serial bus and the data transmission protocol for standard
2
C specification 2.0. The PCM1681 and PCM1681-Q1
2
C control interface is available when MSEL (pin 14) is tied with
1
1
8
9
1−8
9
ACK
DATA
ACK
Read Operation if 1; Otherwise, Write Operation
M
S
M
S
W
ACK
DATA
ACK
M
S
S
M
R
ACK
DATA
ACK
2
Figure 28. Basic I
C Framework
Product Folder Link(s):
PCM1681 PCM1681-Q1
PCM1681
PCM1681-Q1
SLES211B – FEBRUARY 2008 – REVISED JUNE 2008
LSB
0
ADR
R/W
1−8
9
9
Sp
DATA
ACK
ACK
Stop
Condition
M
S
S
M
DATA
ACK
ACK
Sp
S
M
M
M
DATA
ACK
NACK
Sp
T0049-01
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