The PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages

PCM1681

Manufacturer Part NumberPCM1681
DescriptionThe PCM1681 and PCM1681-Q1 are CMOS monolithic integrated circuits which feature an eight-channel 24-bit audio digital-to-analog converter (DAC) and support circuitry in small 28-lead TSSOP PowerPAD packages
ManufacturerTexas Instruments
PCM1681 datasheet
 


Specifications of PCM1681

# Dacs8# Inputs / # Outputs0 / 8
ArchitectureCurrent Segment DACResolution(bits)24
Sampling Rate(max)(khz)200Control InterfaceSPI, I2C,H/W
Digital Audio InterfaceL,R,I2S,TDM,DSPThd+n(typ)(%)0.002
Dac Snr(typ)(db)105Power Consumption(typ)(mw)386
Operating Temperature Range(c)-40 to 85Analog Voltage Av/dd(min)(v)4.5
Analog Voltage Av/dd(max)(v)5.5Pin/package28HTSSOP
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PCM1681
PCM1681-Q1
SLES211B – FEBRUARY 2008 – REVISED JUNE
2008....................................................................................................................................................
WRITE OPERATION
A master can write to any PCM1681 and PCM1681-Q1 registers using a single access. The master sends a
PCM1681 or PCM1681-Q1 slave address with a write bit, a register address, and the data. When undefined
registers are accessed, the PCM1681 or PCM1681-Q1 sends an acknowledgement, but the write operation does
not occur.
Figure 29
is a diagram of the write operation.
Transmitter
M
M
Data Type
St
Slave Address
M: Master Device S: Slave Device
St: Start Condition W: Write ACK: Acknowledge Sp: Stop Condition
READ OPERATION
A master can read any PCM1681 or PCM1681-Q1 register using a single access. The master sends a PCM1681
or PCM1681-Q1 slave address with a read bit after transferring the register address. Then the PCM1681 or
PCM1681-Q1 transfers the data in the register specified.
Transmitter
M
M
M
Data Type
St
Slave Address
W
M: Master Device S: Slave Device St: Start Condition
Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge
W: Write R: Read
NOTE: The slave address after the repeated start condition must be the same as the previous slave address.
24
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M
S
M
W
ACK
Reg Address
ACK
Figure 29. Write Operation
Figure 30
is a diagram of the read operation.
S
M
S
M
ACK
Reg Address
ACK
Sr
Slave Address
Figure 30. Read Operation
Product Folder Link(s):
PCM1681 PCM1681-Q1
www.ti.com
S
M
S
M
Write Data
ACK
Sp
R0002-01
M
M
S
S
M
R
ACK
Read Data
NACK
R0002-02
Copyright © 2008, Texas Instruments Incorporated
M
Sp