The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages

PCM1772

Manufacturer Part NumberPCM1772
DescriptionThe PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages
ManufacturerTexas Instruments
PCM1772 datasheet
 


Specifications of PCM1772

# Dacs2# Inputs / # Outputs0 / 2
ArchitectureMultilevel Delta-SigmaResolution(bits)24
Sampling Rate(max)(khz)48Control InterfaceSPI
Digital Audio InterfaceL,R,I2SThd+n(typ)(%)0.007
Dac Snr(typ)(db)98Power Consumption(typ)(mw)6.5
Operating Temperature Range(c)0 to 70Analog Voltage Av/dd(min)(v)1.6
Analog Voltage Av/dd(max)(v)3.6Pin/package16TSSOP, 20VQFN
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Burr Brown Products
from Texas Instruments
LOW-VOLTAGE AND LOW-POWER STEREO AUDIO
DIGITAL-TO-ANALOG CONVERTER WITH LINEOUT AMPLIFIER
FEATURES
Multilevel DAC Including Lineout Amplifier
Analog Performance (V
, V
CC1
– Dynamic Range: 98 dB Typ
– THD+N at 0 dB: 0.007% Typ
1.6-V to 3.6-V Single Power Supply
Low Power Dissipation:
6 mW at V
, V
= 2.4 V
CC1
CC2
System Clock: 128 f
, 192 f
S
S
Sampling Frequency: 5 kHz to 50 kHz
Software Control (PCM1772):
– 16-, 20-, 24-Bit Word Available
– Left-, Right-Justified, and I
– Slave/Master Selectable
– Digital Attenuation: 0 dB to –62 dB,
1 dB/Step
– 44.1-kHz Digital De-Emphasis
– Zero Cross Attenuation
– Digital Soft Mute
– Monaural Analog-In With Mixing
– Monaural Speaker Mode
Hardware Control (PCM1773):
2
– Left-Justified and I
S
– 44.1-kHz Digital De-Emphasis
– Monaural Analog-In With Mixing
Pop-Noise-Free Circuit
3.3-V Tolerant
Packages: TSSOP-16 and VQFN-20
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
APPLICATIONS
Portable Audio Player
Cellular Phone
= 2.4 V):
CC2
PDA
Other Applications Requiring Low-Voltage
Operation
DESCRIPTION
The PCM1772 and PCM1773 devices are CMOS,
, 256 f
, 384 f
monolithic, integrated circuits which include stereo
S
S
digital-to-analog converters, lineout circuitry, and
support circuitry in small TSSOP-16 and VQFN-20
packages.
The data converters use TI's enhanced multilevel -
2
S
architecture, which employs noise shaping and
multilevel amplitude quantization to achieve excellent
dynamic performance and improved tolerance to
clock jitter. The PCM1772 and PCM1773 devices
accept several industry standard audio data formats
with 16- to 24-bit data, left-justified, I
providing easy interfacing to audio DSP and decoder
devices. Sampling rates up to 50 kHz are supported.
A full set of user-programmable functions is
accessible through a 3-wire serial control port, which
supports register write functions.
PCM1772, PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
2
S, etc.,
Copyright © 2001–2007, Texas Instruments Incorporated

PCM1772 Summary of contents

  • Page 1

    ... The PCM1772 and PCM1773 devices accept several industry standard audio data formats with 16- to 24-bit data, left-justified, I providing easy interfacing to audio DSP and decoder devices ...

  • Page 2

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted ...

  • Page 3

    ... OUT CC1 AIN = 0.56 V (peak-to-peak) CC2 at 20 kHz Submit Documentation Feedback PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 and 24-bit data unless S L PCM1772PW, PCM1773PW, PCM1772RGA, PCM1773RGA MIN TYP MAX 128 f , 192 f , 256 f , 384 ...

  • Page 4

    ... NC – No internal connection 44.1 kHz, system clock = 256 f CC2 S TEST CONDITIONS BPZ input BPZ input (4) Power down BPZ input (4) Power down PCM1772PW, -73PW: 16-terminal TSSOP PCM1772RGA, -73RGA: 20-terminal VQFN 16 SCKI LRCK 15 MS DATA 14 MC BCK AGND1 CC1 ...

  • Page 5

    ... Mode control port serial data input. Controls the operation mode on the PCM1772 device Mode control port select. The control port is active when this terminal is low Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input V 12 — ...

  • Page 6

    ... Mode control port select. The control port is active when this terminal is low 17, — No connect 18 Reset input. When low, the PCM1772 device is powered down, and all mode control registers are reset to default settings. SCKI 16 I System clock input V 12 — ...

  • Page 7

    ... L-channel analog signal output of the lineout amplifiers OUT R-channel analog signal output of the lineout amplifiers OUT SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 DESCRIPTION . CC1 . CC2 nominal. CC2 DESCRIPTION . CC1 . CC2 nominal. CC2 Submit Documentation Feedback PCM1772, PCM1773 . CC1 . CC1 7 ...

  • Page 8

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 LRCK Audio DATA Interface BCK (FMT) MS SPI (AMIX) MC Port (DEMP) MD Clock Manager SCKI ( ) : PCM1773 All specifications 25° CC1 DIGITAL FILTER Digital Filter (De-Emphasis Off) AMPLITUDE vs FREQUENCY 0 −20 −40 −60 − ...

  • Page 9

    ... S G003 104 102 100 3.2 3.6 4.0 1.2 G005 Submit Documentation Feedback PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 and 24-bit data unless S L DE-EMPHASIS ERROR vs FREQUENCY – Frequency – kHz Figure 4. DYNAMIC RANGE ...

  • Page 10

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications 25° CC1 otherwise noted. SIGNAL-TO-NOISE RATIO vs SUPPLY VOLTAGE 104 102 100 1.2 1.6 2.0 2.4 2.8 V – Supply Voltage – Figure 7. TOTAL HARMONIC DISTORTION + NOISE ...

  • Page 11

    ... G013 Submit Documentation Feedback PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 and 24-bit data unless S L CHANNEL SEPARATION vs FREE-AIR TEMPERATURE − – Free-Air Temperature – Figure 12. SUPPLY CURRENT vs SAMPLING FREQUENCY ...

  • Page 12

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications 25° CC1 otherwise noted. OUTPUT SPECTRUM (–60 dB 8192) 0 −20 −40 −60 −80 −100 −120 −140 – Frequency – kHz Figure 16. ...

  • Page 13

    ... System Clock, Reset, and Functions System Clock Input The PCM1772 and PCM1773 devices require a system clock for operating the digital interpolation filters and multilevel - modulators. The system clock is applied at terminal 16 (SCKI). clock frequencies for common audio sampling rates. Figure 18 shows the timing requirements for the system clock input ...

  • Page 14

    ... SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 Power On/Off and Reset The PCM1772/73 always must have the PD pin set from LOW to HIGH once after power-supply voltages V and V have reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied CC2 for the power-on sequence ...

  • Page 15

    ... Power-Up/-Down Sequence and Reset The PCM1772 device has two kinds of power-up/-down methods: the PD terminal through hardware control and PWRD (register 4, B0) through software control. The PCM1773 device has only the PD terminal through hardware control for the power-up/-down sequence. The power-up or power-down sequence operates the same as the power-on or power-off sequence ...

  • Page 16

    ... Data formats are selected using the format bits, FMT[2:0] of control register 3 in case of the PCM1772 device, and are selected using the FMT terminal in case of the PCM1773 device. The default data format is 24-bit, left-justified, slave mode. All formats require binary 2s complement, MSB-first audio data ...

  • Page 17

    ... MSB 1/f S L-Channel N−2 N−1 LSB MSB only) S 1/f S L-Channel N−2 N−1 LSB MSB Submit Documentation Feedback PCM1772, PCM1773 R-Channel LSB MSB LSB MSB LSB LSB R-Channel N−2 N− ...

  • Page 18

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 LRCK (Input) t (BCH) BCK (Input) t (BCY) DATA t (DS) PARAMETERS BCK pulse cycle time BCK high-level time BCK low-level time BCK rising edge to LRCK edge LRCK edge to BCK rising edge DATA setup time ...

  • Page 19

    ... S S Figure 24. Audio Interface Timing (Master Mode) SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 t (DL) t (BCL) t (DB) t (DH) SYMBOL Submit Documentation Feedback PCM1772, PCM1773 50 50 (DB T0011-01 MIN MAX (1) t 1/(256 f ) (SCY) ...

  • Page 20

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 Hardware Control (PCM1773) The digital functions of the PCM1773 device are capable of hardware control. Table 4 shows de-emphasis control, and DEMP 20 Table 5 shows analog mixing control. Table 3. Data Format Select FMT DATA FORMAT ...

  • Page 21

    ... Software Control (PCM1772) The PCM1772 device has many programmable functions that can be controlled in the software control mode. The functions are controlled by programming the internal registers using MS, MC, and MD. The software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface. ...

  • Page 22

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 Control Interface Timing Requirements (PCM1772) Figure 27 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation (MLS) t (MCH (MDS) PARAMETERS ...

  • Page 23

    ... Mode Control Registers (PCM1772) User-Programmable Mode Controls The PCM1772 device has a number of user-programmable functions that can be accessed via mode control registers. The registers are programmed using the serial control interface, as discussed in the Software Control (PCM1772) section. Table 6 lists the available mode control functions, along with their reset default conditions and associated register index ...

  • Page 24

    ... PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 Register Definitions B15 B14 B13 B12 B11 0 IDX6 IDX5 IDX4 IDX3 IDX[6:0]: 000 0001b MUTx: Soft Mute Control Where corresponding to the line output V Default Value: 0 MUTL, MUTR = 0 Mute disabled (default) ...

  • Page 25

    ... B7 B6 IDX2 IDX1 IDX0 OVER RSV oversampling , 384f oversampling OUT 2 S format Submit Documentation Feedback PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 RINV AMIX DEM FMT2 FMT1 R. This function can be used to OUT L/V R) internally. OUT OUT ...

  • Page 26

    ... PWRD = 1 Power-down state This bit is used to enter into low-power mode. Note that PWRD has no reset function. When this bit is set to 1, the PCM1772 device enters low-power mode, and all digital circuits are reset except the register states, which remain unchanged. 26 Register 04 ...

  • Page 27

    ... Monaural Output (BTL Mode/Monaural Speaker) When the user needs monaural output, the PCM1772 device can provide it. The PCM1772 device has RINV bit on control register 03. Because this bit allows the user to invert the polarity of the line output for the right channel, the user can create a monaural output by summing the line output for left and right channels through the external power amplifier or headphone amplifier ...

  • Page 28

    ... Power Supplies and Grounding The PCM1772 and PCM1773 devices require a 2.4-V typical analog supply for V supplies power the DAC, analog output filter, and other circuits. For best performance, these 2.4-V supplies ...

  • Page 29

    ... BCK for data formats (2), (3), and (4) In Figure 29, changed signal direction on SCKI pin Revision History .......................................................................................... ......................................................................................................................... 28 .................................................................................................... ..................................................................................................... ...................................................................................................................................... 1 ............................................................................................................................. 2 sheet................................................................................. 2 ................................................................................................................ 5 and Figure 14.............................................................................................................. 11 ........................................................................................................... 28 Submit Documentation Feedback PCM1772, PCM1773 SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007 ................................................................ 28 ........................... 3 ................................................ 2 ................................................... 17 Page Page Page 29 ...

  • Page 30

    ... PACKAGING INFORMATION (1) Orderable Device Status PCM1772PW ACTIVE PCM1772PWG4 ACTIVE PCM1772PWR ACTIVE PCM1772PWRG4 ACTIVE PCM1772RGA ACTIVE PCM1772RGAG4 ACTIVE PCM1772RGAR ACTIVE PCM1772RGARG4 ACTIVE PCM1773PW ACTIVE PCM1773PWG4 ACTIVE PCM1773PWR ACTIVE PCM1773PWRG4 ACTIVE PCM1773RGA ACTIVE PCM1773RGAG4 ACTIVE PCM1773RGAR ACTIVE PCM1773RGARG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs ...

  • Page 31

    MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date ...

  • Page 32

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing PCM1772PWR TSSOP PW PCM1772RGAR VQFN RGA PCM1773PWR TSSOP PW PCM1773RGAR VQFN RGA PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 16 2000 330.0 17.4 6.8 20 2000 330.0 13.4 4.4 16 2000 330 ...

  • Page 33

    ... Device Package Type PCM1772PWR TSSOP PCM1772RGAR VQFN PCM1773PWR TSSOP PCM1773RGAR VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 RGA 20 2000 PW 16 2000 RGA 20 2000 Pack Materials-Page 2 31-Jul-2009 Width (mm) Height (mm) 346.0 346.0 33.0 346.0 346 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...