The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages

PCM1772

Manufacturer Part NumberPCM1772
DescriptionThe PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages
ManufacturerTexas Instruments
PCM1772 datasheet
 


Specifications of PCM1772

# Dacs2# Inputs / # Outputs0 / 2
ArchitectureMultilevel Delta-SigmaResolution(bits)24
Sampling Rate(max)(khz)48Control InterfaceSPI
Digital Audio InterfaceL,R,I2SThd+n(typ)(%)0.007
Dac Snr(typ)(db)98Power Consumption(typ)(mw)6.5
Operating Temperature Range(c)0 to 70Analog Voltage Av/dd(min)(v)1.6
Analog Voltage Av/dd(max)(v)3.6Pin/package16TSSOP, 20VQFN
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PCM1772, PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
Power On/Off and Reset
The PCM1772/73 always must have the PD pin set from LOW to HIGH once after power-supply voltages V
and V
have reached the specified voltage range and stable clocks SCKI, BCK, and LRCK are being supplied
CC2
for the power-on sequence. A minimum time of 1 ms after both the clock and power-supply requirements are
met is required before the PD pin changes from LOW to HIGH, as shown in
LOW-to-HIGH transition, the internal logic state is held in reset for 1024 system clock cycles prior to the start of
the power-on sequence. During the power-on sequence, V
reaching an output level that corresponds to the input data after a period of 9334/f
pin is set from HIGH to LOW first. Then V
9334/f
, as shown in
Figure
20, after which power can be removed without creating pop noise. When powering
S
on or off, adhering to the timing requirements of
If the timing requirements are not met, pop noise might occur.
V
, V
CC1
CC2
0 V
LRCK, BCK, SCKI
PD
Internal Reset
0 V
V
L, V
R
OUT
OUT
V
, V
CC1
CC2
LRCK, BCK, SCKI
PD
V
L, V
R
OUT
OUT
14
L and V
OUT
OUT
L and V
R decrease gradually to ground level over a period of
OUT
OUT
Figure 19
and
Figure 20
1 ms (Min)
1 ms (Min)
Figure 19. Power-On Sequence
9334/f
Figure 20. Power-Off Sequence
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Figure
19. Subsequent to the PD
R increase gradually from ground level,
. When powering off, the PD
S
ensures that pop noise does not occur.
1024 Internal System Clocks
9334/f
S
T0006-01
0 V
S
0 V
T0007-01
CC1