The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages

PCM1772

Manufacturer Part NumberPCM1772
DescriptionThe PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages
ManufacturerTexas Instruments
PCM1772 datasheet
 


Specifications of PCM1772

# Dacs2# Inputs / # Outputs0 / 2
ArchitectureMultilevel Delta-SigmaResolution(bits)24
Sampling Rate(max)(khz)48Control InterfaceSPI
Digital Audio InterfaceL,R,I2SThd+n(typ)(%)0.007
Dac Snr(typ)(db)98Power Consumption(typ)(mw)6.5
Operating Temperature Range(c)0 to 70Analog Voltage Av/dd(min)(v)1.6
Analog Voltage Av/dd(max)(v)3.6Pin/package16TSSOP, 20VQFN
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PCM1772, PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
Audio Serial Interface
The audio serial interface for the PCM1772 and PCM1773 devices consists of a 3-wire synchronous serial port.
It includes terminals 1 (LRCK), 2 (DATA), and 3 (BCK). BCK is the serial audio bit clock, and it clocks the serial
data present on DATA into the audio interface serial shift register. Serial data is clocked into the PCM1772 and
PCM1773 devices on the rising edge of BCK. LRCK is the serial audio left/right word clock. It latches serial data
into the serial audio interface internal registers.
Both LRCK and BCK of the PCM1772 device support the slave and master modes, which are set by FMT
(register 3). LRCK and BCK are outputs during the master mode and inputs during the slave mode.
In slave mode, BCK and LRCK are synchronous to the audio system clock, SCKI. Ideally, it is recommended
that LRCK and BCK be derived from SCKI. LRCK is operated at the sampling frequency, f
operated at 32, 48, and 64 times the sampling frequency.
In master mode, BCK and LRCK are derived from the system clock, and these terminals are outputs. The BCK
and LRCK are synchronous to SCKI. LRCK is operated at the sampling frequency, f
64 times the sampling frequency.
The PCM1772 and PCM1773 devices operate under LRCK, synchronized with the system clock. The PCM1772
and PCM1773 devices do not need a specific phase relationship between LRCK and the system clock, but do
require the synchronization of LRCK and the system clock. If the relationship between the system clock and
LRCK changes more than ±3 BCK during one sample period, internal operation of the PCM1772 and PCM1773
devices halts within 1/f
, and the analog output is kept in last data until resynchronization between system clock
S
and LRCK is completed.
Audio Data Formats and Timing
The PCM1772 device supports industry-standard audio data formats, including standard, I
The PCM1773 device supports the I
data interface.
Figure 22
shows the data formats. Data formats are selected using the format bits, FMT[2:0] of
control register 3 in case of the PCM1772 device, and are selected using the FMT terminal in case of the
PCM1773 device. The default data format is 24-bit, left-justified, slave mode. All formats require binary 2s
complement, MSB-first audio data.
slave mode.
Figure 24
shows a detailed timing diagram for the serial audio interface in master mode.
AUDIO-DATA INTERFACE FEATURE
Audio data interface format
Audio data bit length
Audio data format
16
2
S and left-justified data formats.
Figure 23
shows a detailed timing diagram for the serial audio interface in
Table 2. Audio Data Interface
PCM1772
PCM1773
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. BCK can be
S
. BCK can be operated at
S
2
S, and left justified.
Table 2
lists the main features of the audio
CHARACTERISTIC
2
Standard, I
S, left-justified
2
I
S, left-justified
16-, 20-, 24-bit, selectable
MSB first, 2s complement