The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages

PCM1772

Manufacturer Part NumberPCM1772
DescriptionThe PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages
ManufacturerTexas Instruments
PCM1772 datasheet
 


Specifications of PCM1772

# Dacs2# Inputs / # Outputs0 / 2
ArchitectureMultilevel Delta-SigmaResolution(bits)24
Sampling Rate(max)(khz)48Control InterfaceSPI
Digital Audio InterfaceL,R,I2SThd+n(typ)(%)0.007
Dac Snr(typ)(db)98Power Consumption(typ)(mw)6.5
Operating Temperature Range(c)0 to 70Analog Voltage Av/dd(min)(v)1.6
Analog Voltage Av/dd(max)(v)3.6Pin/package16TSSOP, 20VQFN
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Software Control (PCM1772)
The PCM1772 device has many programmable functions that can be controlled in the software control mode.
The functions are controlled by programming the internal registers using MS, MC, and MD.
The software control interface is a 3-wire serial port that operates asynchronously to the serial audio interface.
The serial control interface is used to program the on-chip mode registers. MD is the serial data input, used to
program the mode registers. MC is the serial bit clock, used to shift data into the control port. MS is the mode
control port select signal.
Register Write Operation (PCM1772)
All write operations for the serial control port use 16-bit data words.
format. The most significant bit must be 0. Seven bits, labeled IDX[6:0], set the register index (or address) for
the write operation. The eight least significant bits, D[7:0], contain the data to be written to the register specified
by IDX[6:0].
Figure 26
shows the functional timing diagram for writing to the serial control port. To write data into the mode
register, data is clocked into an internal shift register on the rising edge of the MC clock. Serial data can change
on the falling edge of the MC clock and must be stable on the rising edge of the MC clock. The MS signal must
be low during the write mode, and the rising edge of the MS signal must be aligned with the falling edge of the
last MC clock pulse in the 16-bit frame. The MC clock can run continuously between transactions while the MS
signal is low.
MSB
0 0
0
IDX6
IDX5
IDX4
IDX3
Register Index (or Address)
Figure 25. Control Data Word Format for MD
(1) Single Write Operation
MS
MC
MD
MSB
(2) Continuous Write Operation
MS
MC
MD
MSB
IDX2
IDX1
IDX0
D7
D6
16 Bits
LSB
16 Bits x N Frames
LSB
MSB
LSB
N Frames
Figure 26. Register Write Operation
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PCM1772, PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
Figure 25
shows the control data word
D5
D4
D3
D2
D1
D0
Register Data
MSB
MSB
LSB
T0012-01
LSB
R0001-01
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