The PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages

PCM1772

Manufacturer Part NumberPCM1772
DescriptionThe PCM1772 and PCM1773 devices are CMOS, monolithic, integrated circuits which include stereo digital-to-analog converters, lineout circuitry, and support circuitry in small TSSOP-16 and VQFN-20 packages
ManufacturerTexas Instruments
PCM1772 datasheet
 


Specifications of PCM1772

# Dacs2# Inputs / # Outputs0 / 2
ArchitectureMultilevel Delta-SigmaResolution(bits)24
Sampling Rate(max)(khz)48Control InterfaceSPI
Digital Audio InterfaceL,R,I2SThd+n(typ)(%)0.007
Dac Snr(typ)(db)98Power Consumption(typ)(mw)6.5
Operating Temperature Range(c)0 to 70Analog Voltage Av/dd(min)(v)1.6
Analog Voltage Av/dd(max)(v)3.6Pin/package16TSSOP, 20VQFN
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Mode Control Registers (PCM1772)
User-Programmable Mode Controls
The PCM1772 device has a number of user-programmable functions that can be accessed via mode control
registers. The registers are programmed using the serial control interface, as discussed in the Software Control
(PCM1772) section.
Table 6
lists the available mode control functions, along with their reset default conditions
and associated register index.
Register Map
Table 7
shows the mode control register map. Each register includes an index (or address) indicated by the
IDX[6:0] bits.
Table 6. User-Programmable Mode Controls
FUNCTION
Soft mute control, L/R independently
Digital attenuation level setting, 0 dB to –62 dB in 1-dB steps, L/R
independently
Oversampling rate control (128 f
, 192 f
S
S
Polarity control for analog output for R-channel DAC
Analog mixing control for analog in, AIN (terminal 14)
44.1-kHz de-emphasis control
Audio data format select
Zero cross attenuation
Power-down control
Register
IDX
B15
B14
B13
[6:0]
(B14-
B8)
Register 01
01h
0
IDX6
IDX5
Register 02
02h
0
IDX6
IDX5
Register 03
03h
0
IDX6
IDX5
Register 04
04h
0
IDX6
IDX5
(1) RSV: Reserved for test operation. It must be set to 0 during regular operation.
RESET DEFAULT
Disabled
, 256 f
, 384 f
)
128 f
S
S
S
Not inverted
Disabled
Disabled
24-bit, left-justified format
Disabled
Disabled
Table 7. Mode Control Register Map
B12
B11
B10
B9
B8
B7
IDX4
IDX3
IDX2
IDX1
IDX0
MUTR
(1)
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
IDX4
IDX3
IDX2
IDX1
IDX0
OVER
(1)
IDX4
IDX3
IDX2
IDX1
IDX0
RSV
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PCM1772, PCM1773
SLES010G – SEPTEMBER 2001 – REVISED MARCH 2007
REGISTER NO.
01
MUTL, MUTR
0 dB
01, 02
ATL[5:0], ATR[5:0]
oversampling
03
03
03
03
03
04
04
B6
B5
B4
B3
B2
MUTL
ATL5
ATL4
ATL3
ATL2
(1)
RSV
ATR5
ATR4
ATR3
ATR2
(1)
RSV
RINV
AMIX
DEM
FMT2
(1)
(1)
(1)
(1)
RSV
RSV
ZCAT
RSV
RSV
BIT(S)
OVER
RINV
AMIX
DEM
FMT[2:0]
ZCAT
PWRD
B1
B0
ATL1
ATL0
ATR1
ATR0
FMT1
FMT0
(1)
RSV
PWRD
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