PCM1774

Manufacturer Part NumberPCM1774
DescriptionThe PCM1774 is a low-power stereo DAC designed for portable digital audio applications
ManufacturerTexas Instruments
PCM1774 datasheet
 


Specifications of PCM1774

# Dacs2# Inputs / # Outputs0 / 2
ArchitectureDelta-SigmaResolution(bits)16
Sampling Rate(max)(khz)50Control InterfaceSPI, I2C
Digital Audio InterfaceL,R,I2S,DSPThd+n(typ)(%)0.002
Dac Snr(typ)(db)93Power Consumption(typ)(mw)7
Additional FeaturesHeadphone, MixOperating Temperature Range(c)-40 to 85
Analog Voltage Av/dd(min)(v)2.4Analog Voltage Av/dd(max)(v)3.6
Io Supply(min)(v)1.71Io Supply(max)(v)3.6
Pin/package20QFN  
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Burr Brown Products
from Texas Instruments
16-Bit, Low-Power Stereo Audio DAC With Analog Mixing, Line and Headphone Outputs
FEATURES
Analog Front End:
– Stereo Single-Ended Input
– Microphone Amplifier (12 dB, 20 dB)
Analog Back End:
– Stereo/Mono Line Output With Volume
– Stereo/Mono Headphone Amplifier With
Volume
Analog Performance:
– Dynamic Range: 93 dB
– 40-mW + 40-mW Headphone Output at
R
= 16
L
Power Supply Voltage
– 1.71 V to 3.6 V for Digital I/O Section
– 1.71 V to 3.6 V for Digital Core Section
– 2.4 V to 3.6 V for Analog Section
– 2.4 V to 3.6 V for Power Amplifier Section
Low Power Dissipation:
– 6.4 mW in Playback, 1.8 V/2.4 V, 44.1 kHz
– 3.3 μW in Power Down
Sampling Frequency: 5 kHz to 50 kHz
Operation From a Single Clock Input Without
PLL
System Clock:
– Common-Audio Clock (256 f
13/26, 13.5/27, 19.2/38.4, 19.68/39.36 MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
2
2 (I
C™) or 3 (SPI) Wire Serial Control
Programmable Function by Register Control:
– Digital Attenuation: 0 dB to –62 dB
– Digital Gain of DAC: 0, 6, 12, 18 dB
– Power Up/Down Control for Each Module
– 6-dB to –70-dB Gain for Analog Outputs
– 0/12/20 dB for Microphone Input
– 0-dB to –21-dB Gain for Analog Mixing
– Three-Band Tone Control and 3D Sound
– Analog Mixing Control
Pop-Noise Reduction Circuit
Short Protection Circuit
Package: 4-mm
Operation Temperature Range: –40 C to 85 C
APPLICATIONS
Portable Audio Player, Cellular Phone
Video Camcorder, Digital Still Camera
PMP/DMB/PND
DESCRIPTION
The PCM1774 is a low-power stereo DAC designed
for portable digital audio applications. The device
integrates headphone amplifier, line amplifier, line
input, boost amplifier, programmable gain control,
analog mixing, and sound effects. It is available in a
/384 f
), 12/24,
S
S
small-footprint, 4-mm
PCM1774 supports right-justified, left-justified, I
and DSP formats, providing easy interfacing to audio
DSP and decoder/encoder chips. Sampling rates up
to 50 kHz are supported. The user-programmable
functions are accessible through a two- or three-wire
serial control port.
PCM1774
SLAS551 – JULY 2007
4-mm QFN Package
4-mm QFN package. The
2
Copyright © 2007, Texas Instruments Incorporated
S,

PCM1774 Summary of contents

  • Page 1

    ... Portable Audio Player, Cellular Phone Video Camcorder, Digital Still Camera PMP/DMB/PND DESCRIPTION The PCM1774 is a low-power stereo DAC designed for portable digital audio applications. The device integrates headphone amplifier, line amplifier, line input, boost amplifier, programmable gain control, analog mixing, and sound effects available in a ...

  • Page 2

    ... PCM1774 SLAS551 – JULY 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications ...

  • Page 3

    ... EIAJ, A-weighted EIAJ, A-weighted 0 dB EIAJ, A-weighted 30 mW volume = mW volume = –1 dB Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 , and 16-bit data (unless S MIN TYP MAX UNIT left-, right-justified, DSP 16 MSB first, 2s complement ...

  • Page 4

    ... PCM1774 SLAS551 – JULY 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications otherwise noted). PARAMETER Load resistance PSRR Power-supply rejection ratio Line Input to Headphone Output Through Mixing Path (HPOL and HPOR ALC = OFF, volume = 0 dB, speaker = powered down, analog mixing = enabled, not capless mode ...

  • Page 5

    ... Mode control select for three-wire/two-wire interface Ground for speaker power amplifier System clock Analog power supply Analog common voltage Power supply for digital core Power supply for digital I/O Power supply for power amplifier Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 BCK 10 SCKI 9 DGND 8 V ...

  • Page 6

    ... PCM1774 SLAS551 – JULY 2007 FUNCTIONAL BLOCK DIAGRAM 6 Submit Documentation Feedback www.ti.com ...

  • Page 7

    ... TREBLE) Figure 3. TYPICAL PERFORMANCE CURVES = 3 kHz, system clock = 256 otherwise noted. 0.2 0.1 0 -0.1 -0 Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 , and 16-bit data, unless S INTERPOLATION FILTER, PASS BAND 0.1 0.2 0.3 0 Frequency - xf s Figure 2. THREE-BAND TONE CONTROL (BASS) Figure 4. 0.5 7 ...

  • Page 8

    ... PCM1774 SLAS551 – JULY 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications otherwise noted. THREE-BAND TONE CONTROL (MIDRANGE) Figure 5. THD+N/SNR vs POWER SUPPLY DAC TO HEADPHONE OUTPUT, 16- 0. kHz IN 0.04 THD+N 0.03 0.02 SNR 0. 2.5 3 Power Supply - V Figure 3 kHz, system clock = 256 f ...

  • Page 9

    ... OUTPUT SPECTRUM (DAC TO HEADPHONE OUTPUT, 0 -20 -40 -60 -80 3.6 V -100 -120 -140 Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 , and 16-bit data, unless S THD+N vs OUTPUT POWER (HEADPHONE, 16- , VOLUME = 6 dB kHz 2.4 V 3.3 V 3 100 P - Output Power - mW O Figure 10. ...

  • Page 10

    ... V COM recommended that a 4.7-μF capacitor be connected between this pin and AGND to provide clean voltage and avoid pop noise. The PCM1774 may have a little pop noise on each analog output if a capacitor smaller than 4.7 μF is used. Line Output The HPOL/LOL and HPOR/LOR pins can drive a 10-k monaural single-ended, monaural differential, or stereo single-line output with 1-Vrms output. These outputs include an analog volume amplifier that can be set from – ...

  • Page 11

    ... PGND, or any two outputs are shorted together. When the short circuit is detected PA on the outputs, the PCM1774 powers down the shorted amplifier immediately. The short-protection status can be monitored by reading register 77 (STHC, STHL, SCHR) through the I operates in any enabled headphone amplifier. ...

  • Page 12

    ... SLAS551 – JULY 2007 DESCRIPTION OF OPERATION System Clock Input The PCM1774 can accept clocks of various frequencies without a PLL. They are used for clocking the digital filters and automatic level control and delta-sigma modulators and are classified as common-audio and application-specific clocks. Table 2 Figure 13 shows the timing requirements for system clock inputs ...

  • Page 13

    ... Power supply sequencing is not required recommended to turn off all power supplies after setting the registers with the system clock input. Power-Supply Current The current consumption of the PCM1774 depends on power up/down status of each circuit module. In order to reduce the power consumption, disabling each module is recommended when it is not used in an application or operation. ...

  • Page 14

    ... PCM1774 SLAS551 – JULY 2007 OPERATION MODE All Power Down All Active Line Output Headphone Output Headphone Output with Sound Effect Headphone Output with Stereo Analog Mixing Headphone Output with Mono Analog Mixing 14 Table 5. Power Consumption Table CONDITION V POWER SUPPLY CURRENT [mA] ...

  • Page 15

    ... The PCM1774 requires LRCK to be synchronized with the system clock. The PCM1774 does not require a specific phase relationship between LRCK and the system clock. The PCM1774 has both master mode and slave mode interface formats, which can be selected by register 84 (MSTR). In master mode, the PCM1774 generates LRCK and BCK from the system clock. ...

  • Page 16

    ... PCM1774 SLAS551 – JULY 2007 Audio Data Formats and Timing 2 The PCM1774 supports I S, right-justified, left-justified, and DSP formats. The data formats are shown in Figure 16 and are selected using registers 70 and 81 (RFM[1:0], PFM[1:0]). All formats require binary 2s-complement, MSB-first audio data. The default format is I ...

  • Page 17

    ... S S Figure 15. Audio Interface Timing (Master Mode) t (DL w(BCL) (DB (DS) (DH) PARAMETERS Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 50 50 (DB MIN MAX UNIT (1) 1/(256 f ...

  • Page 18

    ... PCM1774 SLAS551 – JULY 2007 (a) Right-Justified Data Format; L-Channel = HIGH, R-Channel = LOW, LRPC = 0 LRCK BCK (= 16-Bit Right-Justified DIN ( Data Format; L-Channel = LOW, R-Channel = HIGH, LRPC = 0 LRCK BCK (= DIN MSB (c) Left-Justified Data Format ...

  • Page 19

    ... Bits LSB MSB 8 Bits x N Frames LSB MSB LSB Register (N) Data Register (N+1) Data N Frames Figure 18. Register Write Operation Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 Figure 17 shows the control data word LSB Register Data R0001-01 MSB ...

  • Page 20

    ... The PCM1774 has its own 7-bit slave address. The first six bits (MSBs) of the slave address are factory preset to 100011. The last bit of the address byte is the device select bit, which can be user-defined by the ADR terminal. A maximum of two PCM1774 can be connected on the same bus at one time. The PCM1774 responds when it receives its own slave address ...

  • Page 21

    ... The master can read PCM1774 register. The value of the register address is stored in an indirect index register in advance. The master sends a PCM1774 slave address with a read bit after storing the register address. Then the PCM1774 transfers the data which the index register specifies. ...

  • Page 22

    ... PCM1774 SLAS551 – JULY 2007 Transmitter Data Type St Slave Address W M: Master Device S: Slave Device St: Start Condition Sr: Repeated Start Condition ACK: Acknowledge Sp: Stop Condition NACK: Not Acknowledge W: Write R: Read NOTE: The slave address after the repeated start condition must be the same as the previous slave address. ...

  • Page 23

    ... RSV GMR2 RSV RSV LPAE RSV RSV RSV RSV RSV RSV 3DEN RSV RSV RSV RSV RSV PTM1 Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 HLV5 HLV4 HLV3 HLV2 HLV1 HRV5 HRV4 HRV3 HRV2 HRV1 ATL5 ATL4 ATL3 ...

  • Page 24

    ... PCM1774 SLAS551 – JULY 2007 Register Definitions Registers 64 and 65 B15 B14 B13 B12 Register 64 0 IDX6 IDX5 IDX4 Register 65 0 IDX6 IDX5 IDX4 IDX[6:0]: 100 0000b (40h): Register 64 IDX[6:0]: 100 0001b (41h): Register 65 HMUL: Analog Mute Control for HPL (Line or Headphone L-Channel) ...

  • Page 25

    ... PMUR are set to 0, the digital data is changed from the mute level to the current attenuation level by a 1-dB step for every 8/f time period. In the PCM1774, audible zipper noise can be reduced by selecting zero-cross S detection (register 86, ZCRS). ...

  • Page 26

    ... OVER: Oversampling Control for Delta-Sigma DAC Default value: 0 This bit is used to control the oversampling rate of delta-sigma DAC. When the PCM1774 operates at low sampling rates (less than 24 kHz) and the SCKI frequency is less than 12.5 MHz, OVER = 1 is recommended. OVER = 0 128 f (default) ...

  • Page 27

    ... IDX3 IDX2 IDX1 IDX0 RSV RSV B11 B10 IDX3 IDX2 IDX1 IDX0 PBIS PDAR Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 RSV RSV RSV RSV PMXR PMXL PDAL RSV PHPR ...

  • Page 28

    ... PCM1774 SLAS551 – JULY 2007 Register 74 B15 B14 B13 B12 Register 74 0 IDX6 IDX5 IDX4 IDX[6:0]: 100 1010b (4Ah): Register 74 HPS[1:0]: Line or Headphone Output Configuration Default value: 00 HPOL/LOL and HPOR/LOR can be configured selected as follows. HPS[1:0] Line or Headphone Output Configuration 0 0 Stereo output (default) ...

  • Page 29

    ... MSTR: Master or Slave Selection for Audio Interface Default value: 0 This bit is used to select either master or slave mode for the audio interface. In master mode, the PCM1774 generates LRCK and BCK from the system clock. In slave mode, it receives LRCK and BCK from another device ...

  • Page 30

    ... PCM1774 SLAS551 – JULY 2007 LRPC: LRCK Polarity Control Default value: 0 This bit is used to reverse L-channel and R-channel audio data. LRPC = 0 LRPC = 1 NPR[5:0]: System Clock Rate Selection Default value: 000000 MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70) Default value: 000 These bits are used to select the system clock rate and the dividing rate of the input system clock ...

  • Page 31

    ... Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 (1) REGISTER SETTINGS BIT CLOCK BCK (f MSR[2:0] NPR[5:0] 010 00 0000 64 011 00 0000 64 100 00 0000 64 ...

  • Page 32

    ... PCM1774 SLAS551 – JULY 2007 Table 10. System Clock Frequency for Application-Specific Clock SYSTEM CLOCK ADC SAMPLING RATE SCK (MHz) ADC 19.2 32 DAC SAMPLING RATE (kHz) DAC f (kHz) S 48.214 (SCK/280) 44.407 (SCK/304) 32.142 (SCK/420) 24.107 (SCK/560) 22.203 (SCK/608) 16.071 (SCK/840) 12 ...

  • Page 33

    ... Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 REGISTER SETTINGS BIT CLOCK BCK (f MSR[2:0] NPR[5:0] 011 01 0110 66 011 01 0101 ...

  • Page 34

    ... If no zero-cross data is input for a 512/f period (10 48-kHz sampling rate), then a time-out occurs and the PCM1774 starts changing the S attenuation, gain, or volume level. The zero-cross detector cannot be used with continuous-zero and dc data. ...

  • Page 35

    ... IDX3 IDX2 IDX1 IDX0 RSV Disable (default) Enable Disable (default) Enable Disable (default) Enable Disable (default) Enable Disable (default) Enable Disable (default) Enable Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 MXR2 MXR1 MXR0 RSV MXL2 MXL1 B0 MXL0 35 ...

  • Page 36

    ... PCM1774 SLAS551 – JULY 2007 Register 89 B15 B14 B13 B12 Register 89 0 IDX6 IDX5 IDX4 IDX[6:0]: 101 1001b (59h): Register 89 GMR[2:0]: Gain Level Control for PG6 (Gain Amplifier for Analog Input or R-Channel Bypass) GML[2:0]: Gain Level Control for PG5 (Gain Amplifier for Analog Input or L-Channel Bypass) Default value: 000 These bits are used for setting the gain level of the analog source to the mixing amplifier ...

  • Page 37

    ... Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 RSV RSV LGA4 LGA3 LGA2 LGA1 TONE CONTROL GAIN (BASS –1 dB –2 dB – ...

  • Page 38

    ... PCM1774 SLAS551 – JULY 2007 Register 93 B15 B14 B13 B12 Register 93 0 IDX6 IDX5 IDX4 IDX[6:0]: 101 1101b (5Dh): Register 93 MGA[4:0]: Middle Boost Gain Control Default value: 0 0000 These bits are used to set the midrange boost gain level for the digital data. The detailed characteristics are ...

  • Page 39

    ... Reserved : : Reserved B11 B10 IDX3 IDX2 IDX1 IDX0 RSV Disable (default) Enable Narrow (default) Wide Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 3DEN RSV 3FL0 3DP3 3DP2 3DP1 B0 3DP0 39 ...

  • Page 40

    ... PCM1774 SLAS551 – JULY 2007 Register 96 B15 B14 B13 B12 Register 96 0 IDX6 IDX5 IDX4 IDX[6:0]: 110 0000b (60h): Register 96 MXEN: Digital Monaural Mixing Default value: 0 This bit is used to enable or disable monaural mixing in the section that combines L-ch data and R-ch data. MXEN = 0 ...

  • Page 41

    ... Do not set. – 10 100 01 250 00 450 11 900 Do not set. – 10 100 01 250 00 450 Submit Documentation Feedback PCM1774 SLAS551 – JULY 2007 PTM0 RES4 RES3 RES2 RES1 POWER-DOWN NOTE TIME [ms] 750 1500 – – 400 750 Default 1500 – ...

  • Page 42

    ... Figure 25. High-Pass Filter for Headphone Output SCKI BCK DD 11 LRCK 5 DGND DIN AGND MS/ADR 3 MD/SDA MC/SCL 1 PCM1774 PGND MODE 20 AIN1L 19 AIN1R 16 V COM HPOL/LOL C 3 HPOR/LOR Figure 24. Connection Diagram Table 12. Recommended External Parts C –C 1 μ 1–4.7 μ 0.1 μ ...

  • Page 43

    ... PCM1774RGPR ACTIVE PCM1774RGPRG4 ACTIVE PCM1774RGPT ACTIVE PCM1774RGPTG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

  • Page 44

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing PCM1774RGPR QFN RGP PCM1774RGPR QFN RGP PCM1774RGPT QFN RGP PCM1774RGPT QFN RGP PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 20 3000 330.0 12.4 4.25 20 3000 330 ...

  • Page 45

    ... Device Package Type PCM1774RGPR QFN PCM1774RGPR QFN PCM1774RGPT QFN PCM1774RGPT QFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGP 20 3000 RGP 20 3000 RGP 20 250 RGP 20 250 Pack Materials-Page 2 17-Dec-2011 Width (mm) Height (mm) 346.0 346.0 29.0 346.0 346 ...

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    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...