The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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216-kHz Digital Audio Interface Transceiver (DIX)
FEATURES
1
• Integrated DIX, ADC, and Signal Routing:
23456
– Asynchronous Operation (DIR, DIT, ADC)
– Mux and Routing of PCM Data:
2
– I
S™, Left-Justified, Right-Justified
– Multipurpose Input/Output Pins
Digital Audio I/F Receiver (DIR):
– 24-bit, 216-kHz Capable
– 50-ps Ultralow Jitter
– Non-PCM Detection (IEC61937, DTS-CD/LD)
– 12x S/PDIF Input Ports:
– 2x Coaxial S/PDIF Inputs
– 10x Optical S/PDIF Inputs
Digital Audio I/F Transmitter (DIT):
– 24-Bit, 216-kHz Capable
– 24-Bit Data Length
– 48-Bit Channel Status Buffer
– Synchronous/Asynchronous Operation
Analog-to-Digital Converter (ADC):
– 24-Bit, 96-kHz Capable
– Dynamic Range: 101 dB (f
– Synchronous/Asynchronous Operation
Routing Function:
– Input: 3x PCM, 1x DIR, 1x ADC
– Output: Main Out, Aux Out, DIT
– Multi-Channel (8-Ch) PCM Routing
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AC-3 is a trademark of Dolby Laboratories.
2
SPI is a trademark of Motorola, Inc.
3
2
2
I
S, I
C are trademarks of NXP Semiconductors.
4
TOSLINK is a trademark of Toshiba Corp.
5
All other trademarks are the property of their respective owners.
6
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
with Stereo ADC and Routing
Check for Samples:
PCM9211
Other Function Features:
– Power Down (Pin and Register Control)
– PCM Port Sampling Frequency Counter
– GPIO and GPO
– OSC for External Crystal (24.576 MHz)
– SPI™, I
Power Supply:
– 3.3 V (2.9 V to 3.6 V) for DIX, All Digital
– 5 V (4.5 V to 5.5 V) for ADC Analog
Operating Temperature: –40°C to +85°C
Package: 48-Pin LQFP
APPLICATIONS
Home Theater and AVR Equipment
Television and Soundbars
Musical Instruments, Recording, and
Broadcast
High-Performance Soundcards
DESCRIPTION
The PCM9211 is a complete analog and digital
front-end
= 96 kHz)
S
recorders.
The PCM9211 integrates a stereo ADC, S/PDIF
transceiver with up to 12 multiplexed inputs and 3x
PCM inputs to allow other audio receivers to be
multiplexed along with the analog and S/PDIF signals
to a digital signal processor (DSP).
PCM9211
SBAS495 – JUNE 2010
2
C™ or Hardware Control Modes
for
today's
multimedia
players
Copyright © 2010, Texas Instruments Incorporated
and

PCM9211 Summary of contents

  • Page 1

    ... Television and Soundbars • Musical Instruments, Recording, and Broadcast • High-Performance Soundcards DESCRIPTION The PCM9211 is a complete analog and digital front-end = 96 kHz) S recorders. The PCM9211 integrates a stereo ADC, S/PDIF transceiver with multiplexed inputs and 3x PCM inputs to allow other audio receivers to be multiplexed along with the analog and S/PDIF signals to a digital signal processor (DSP) ...

  • Page 2

    ... PCM9211 (1) –0 –0 –0 –0 Product Folder Link(s): PCM9211 www.ti.com (1) ORDERING TRANSPORT MEDIA, NUMBER QUANTITY PCM9211PT Tray, 250 PCM9211PTR Tape and Reel, 1000 PCM9211 UNIT –0.3 to +4.0 V –0.3 to +6.5 V ±0.1 V ±0.1 V –0.3 to +6.5 V –0.3 to +6.5 V –0.3 to +6.5 V – ...

  • Page 3

    ... OUT I = –4 mA OUT OUT Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MIN NOM MAX –40 +25 +85 PCM9211 MIN TYP MAX UNIT Left-Justified, Right-Justified 16, 24 Bits MSB first, twos complement 7 216 kHz 7 216 kHz 7 216 kHz 16 ...

  • Page 4

    ... DIR kHz / ADC kHz / DIT f = 192 kHz / DIR kHz / ADC 192 kHz / DIT Full power down, RST = low Product Folder Link(s): PCM9211 www.ti.com PCM9211 MIN TYP MAX UNIT 2.9 3.3 3.6 VDC 2.9 3.3 3.6 VDC 4.5 5.0 5.5 VDC 2.9 3.3 3.6 VDC 4 ...

  • Page 5

    ... TEST CONDITIONS 0.583 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 PCM9211 MIN TYP MAX UNIT 16 24 Bits 16 96 kHz 1.024 6.144 MHz 4.096 24.576 MHz 8.192 24.576 MHz 0 CCAD PP 0 ...

  • Page 6

    ... Submit Documentation Feedback = V = 3.3 V, and unless otherwise noted. DD DDRX CCAD TEST CONDITIONS , measured S / 256f / 512f 256f / 512f S S Product Folder Link(s): PCM9211 www.ti.com PCM9211 MIN TYP MAX UNIT 20 kΩ 0 216 kHz 28 108 kHz 7 216 kHz Level III (± ...

  • Page 7

    ... Multipurpose I/O, Group C (1) Multipurpose I/O, Group C (1) Multipurpose I/O, Group C (1) Multipurpose I/O, Group B (1) Multipurpose I/O, Group B (1) Multipurpose I/O, Group B (1) Multipurpose I/O, Group B No Multipurpose output 0 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 37 36 VDDRX RXIN1 35 RST 34 RXIN2 33 RXIN3 32 RXIN4/ASCKIO 31 RXIN5/ABCKIO 30 RXIN6/ALRCKIO ...

  • Page 8

    ... ADC common voltage output; must connect external decoupling capacitor – Ground, for ADC analog – Power supply, 5.0 V (typ.), for ADC analog No ADC analog voltage input, left channel No ADC analog voltage input, right channel Product Folder Link(s): PCM9211 www.ti.com DESCRIPTION 2 (2) C slave address setting0 2 (2) (3) C data input/output 2 ...

  • Page 9

    ... S POWER SUPPLY DIR DIR ALL ANALOG ANALOG AGNDAD VCC AGND VDDRX GNDRX DVDD DGND Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 RXIN7 SCKO DOUT BCK MAIN OUTPUT LRCK SCKO/ BCK/LRCK PORT DOUT DIT RECOUT0 MPO 0 RECOUT1 MPO0/1 MPO 1 ...

  • Page 10

    ... Product Folder Link(s): PCM9211 www.ti.com , and 24-bit data, unless otherwise noted. S DYNAMIC RANGE AND SNR vs TEMPERATURE Dynamic Range SNR 100 T , Free-Air Temperature ( C) ° A Figure 2. DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE ...

  • Page 11

    ... 100 - 120 - 140 - PASSBAND CHARACTERISTIC 0.1 0 0.1 - 0.2 - 0.3 - 0 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 OUTPUT SPECTRUM (–60 dB 32,768 Frequency (kHz) Figure 6. DECIMATION FILTER 0.2 0.3 0.4 0.5 Normalized Frequency ( Figure 8. Submit Documentation Feedback 11 ...

  • Page 12

    ... Submit Documentation Feedback = 3 kHz, SCK = 512f DD S ANTIALIASING FILTER CHARACTERISTIC 0.3 0 Product Folder Link(s): PCM9211 www.ti.com , and 24-bit data, unless otherwise noted 100 Frequency (kHz) Figure 10. Copyright © 2010, Texas Instruments Incorporated ...

  • Page 13

    ... DSP continues to receive the same system clock. The PCM9211 also has two output ports for the DIR output. The primary output is available from the Main Port and/or MPIO_B; the secondary port is available through MPIO_A. The dividing ratio of BCK and LRCK for the primary output is defined by the DIR ...

  • Page 14

    ... EBU Tech 3250 (also known as AES/EBU) Analog-to-Digital Converter (ADC) The integrated ADC within the PCM9211 is capable of supporting 24-bit data from 16 kHz kHz. The signal-to-noise ratio (SNR) of the ADC module at 96 kHz is 101 dB. The PCM9211 contains integrated front-end buffer amplifiers for the ADC, thereby reducing the need for external amplifiers. The ADC also has several digital features, including digital volume control (adjustable from – ...

  • Page 15

    ... Auxiliary PCM Audio Input and Output (I/O) There are digital auxiliary (AUX) inputs and one AUX output on the PCM9211. These I/Os are multiplexed and shared with RXIN4 through RXIN7, MPIOB, and MPIOC. Each input and output supports a four-wire digital audio interface that is similar to the I (bit clock), LRCK (left/right clock, or word clock) and data transmissions ...

  • Page 16

    ... VCCAD and AGNDAD). Power-Down Function The PCM9211 has a power-down function that is controlled by the external RST pin or a power control register. When the RST pin is held at GND, the PCM9211 powers down. When the device is powered down (that is, RST = GND), all register values are cleared and reset to the respective default values ...

  • Page 17

    ... MPIOs and MPOs Serial I/F Oscillation Circuit Common Supply for ADC Coax Input ( low high, Hi-Z = high impedance. PCM Audio Interface Format Each of the modules in the PCM9211 (DIR, DIT, ADC, Aux I/Os) supports these four interface formats: 2 • 24-bit I S format • 24-bits Left-Justified format • ...

  • Page 18

    ... MSB Left-channel LSB LSB Left-channel LSB LSB Product Folder Link(s): PCM9211 www.ti.com Right-channel LSB Right-channel LSB LSB Right-channel MSB LSB ...

  • Page 19

    ... ADC Details System Clock The system clock for the ADC of the PCM9211 must be either 256f for the ADC (16 kHz to 96 kHz). Table 3 lists the typical system clock frequencies f timing requirements for the system clock inputs. SAMPLING FREQUENCY 16 kHz 32 kHz 44 ...

  • Page 20

    ... During normal ADC operation, the system clock (SCK) is sourced within the PCM9211 (that is, either the DIR SCK, or the oscillator circuit SCK). By running the ADC in Master mode, the ADC can operate from an external SCK source (such as a DSP or PLL circuit), and provide BCK and LRCK to the rest of the PCM9211 circuitry and external components. ...

  • Page 21

    ... Synchronous Clocks 2048/f min S 1024 SCKIx power down t ADCDLY2 1936/f S ZERO Fade Out Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 . Zero crossing detection is S (for example, if there until zero crossing through 255 DEC + t ADCDLY1 ADCDLY2 illustrates the ADC output sequence at ...

  • Page 22

    ... Submit Documentation Feedback Serial Control Mode section. The default mode is slave mode. Master . DOUT changes on the falling edge of BCK. The default timing LRH LRS t DOD DESCRIPTION Product Folder Link(s): PCM9211 www.ti.com 1.4 V 1 MIN TYP MAX UNITS ...

  • Page 23

    ... In master mode, BCK and LRCK are output from the ADC of PCM9211. BCK and LRCK are generated by the internal ADC from SCKI, and BCK is fixed as 64f timing specification is shown in Figure t t BCH BC L BCK (OUTPUT LRCK (OUTPUT) DOUT SYMBOL ...

  • Page 24

    ... PCM9211. The clock source for the external ADC can be selected using Register 42h/ADCLK (the same register that controls the clock source for the internal ADC). To lower power consumption in the PCM9211, the onboard ADC can be set to power-down state using Register 40h/ADDIS. ...

  • Page 25

    ... ADC Level Detect and Interrupt The PCM9211 has the ability to monitor audio inputs, which can be used to trigger interrupt outputs on port INT1. The ADC has a level monitor that can be set so that INT1 can be triggered whenever a specific level (referenced to 0dBFS) is crossed. A block diagram for this function is shown in ...

  • Page 26

    ... EBU Tech 3250 (also known as AES/EBU) In addition, the DIR module within the PCM9211 also meets and exceeds jitter tolerance limits as specified by IEC60958-3 for sampling frequencies between 28 kHz and 216 kHz. Each of the physical connections used for these standards (optical, differential, and single-ended) have different signal levels ...

  • Page 27

    ... PSCKAUTO takes priority over any settings in PSCK[2:0]. PSCK[2:0] only becomes relevant in the system when the PSCKAUTO Register is set to '0'. The PCM9211 can decode S/PDIF input signals between sampling frequencies of 7 kHz and 216 kHz for all PSCK[2:0] settings. The relationship between the output clock (SCKO, BCKO, LRCKO) at the PLL source and ...

  • Page 28

    ... The resistor and capacitors that configure the filter should be located and routed as close as possible to the PCM9211. The external loop filter must be placed on the FILT pins. • The GND node of the external loop filter must be directly connected with AGND pin of the PCM9211; it must be not combined with other signals. Figure 20 shows the configuration of the external loop filter and the connection with the PCM9211 ...

  • Page 29

    ... MPIO_A. Register 24h/XMCKEN controls whether the XMCKO should be muted or not, and Register 24h/XMCKDIV controls the division factor. DIR Data Description Decoded Serial Audio Data Output and Interface Format The PCM9211 supports the following four data formats for the decoded data: • 16-bit MSB First, Right-Justified • ...

  • Page 30

    ... SCKO. Figure 23. DIR Decoded Audio Data Output Timing 30 Submit Documentation Feedback 17±1BCK t SCY t BCL t BCY BCDO DESCRIPTION Product Folder Link(s): PCM9211 www.ti.com Figure 23 illustrates the MIN TYP MAX UNITS 4 CKLR ...

  • Page 31

    ... Channel Status Data, User Data, and Validity Flag The PCM9211 can output decoded channel status data, user data, and a validity flag synchronized with audio data from the input S/PDIF signal. These signals can be transmitted from any of the three MPIOs (MPIO_A, MPIO_B, or MPIO_C) ...

  • Page 32

    ... When set to '00', the device ignores parity errors and continues to output whatever data comes into the device. The setting on '11' is reserved. DIR: Errors and Interrupts The PCM9211 has two pins that are used to inform the system DSP or controller that there is an error interrupt that it should be aware of. The ERR/INT0 and NPCM/INT1 pins can be configured in these ways: ...

  • Page 33

    ... Copyright © 2010, Texas Instruments Incorporated Calculator Complete), INT0 or INT1 performs a bitwise evaluation S Interrupt Source To INTx Mask Bit Figure 27. DIR Interrupt Mask Logic Figure Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 Figure 27 shows the logic that the 28. Hi-Z ERR/INT0 External Pin Hi-Z NPCM/INT1 ...

  • Page 34

    ... If the PLL becomes unlocked, or attempts to run out of range, SFSOUT[3:0] = '0000' is output, and indicates abnormal operation. If the XTI source clock is not supplied before the PCM9211 powers up, SFSOUT [3:0] outputs '0000'. If the XTI source clock is stopped, the f calculator holds its most recent calculated result. Once the XTI source clock is ...

  • Page 35

    ... The Biphase Sampling Frequency Calculator is also used for restricting the type of data that can be received Register 27h/MSK128 is set to '1', the PCM9211 does not accept 128-kHz sampling frequency data 2. If Register 27h/MSK64 is set to '1', the PCM9211 does not accept 64-kHz sampling frequency data. ...

  • Page 36

    ... ADC 001 010 011 Sampling Frequency 100 101 110 DIT 111 is decoded to 4-bit data and stored in the PFSOUT[3:0] register. The input S Product Folder Link(s): PCM9211 www.ti.com Figure 29 illustrates the sampling Audio Port Calculator Copyright © 2010, Texas Instruments Incorporated ...

  • Page 37

    ... Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 PFSOUT1 PFSOUT0 ...

  • Page 38

    ... Lock Normal Operation t CLKST1 DIR Source MUTE DIR Source can be configured using Register 23h/ERRWT[1:0]. t can be configured using Register XTIWT Interrupts; configured by Register 25h) Product Folder Link(s): PCM9211 www.ti.com Non-Biphase Unlock t CLKST2 t XTIWT XTI (ADC) Source MUTE ADC Source . During that ...

  • Page 39

    ... DTSCD, and can also be set in Register 29h/DTS16, 29h/DTS14, and Register 29h/DTSPRD[1:0]. If the PCM9211 detects a Burst Preamble when Non-PCM detection is enabled, an error signal and BPSYNC signal are generated. The BPSYNC signal can be monitored through MPIO_A/MPIO_B/MPIO_C. For more details, see the MPIO section of this document ...

  • Page 40

    ... The PCM9211 has an onboard Digital Audio Interface Transmitter (DIT) that transmits S/PDIF data from 7 kHz to 216 kHz 24-bit audio data. The first 48 bits of the channel status buffer are programmable. The source for the DIT is selectable from the built-in routing function of the PCM9211 as well as the dedicated inputs assigned to the MPIOs. ...

  • Page 41

    ... Data Mute Function The PCM9211 has the ability to mute the audio data on its DIT output. This option is set using Register 62h/TXDMUT. During a mute state (TXDMUT = '1'), the biphase stream continues to flow, but all audio data are zeroed. The channel status data and validity flag are not zeroed. Mute is done at the LRCK edge for both L-ch and R-ch data at the same time ...

  • Page 42

    ... The two multi-purpose outputs (MPO) pins are assigned as MPO0 and MPO1. Assignable Signals for MPIO Pins The PCM9211 has the following signals that can be brought out to MPIOs. Not all MPIOs are equal; be sure to review subsequent sections in this document to see which signals can be brought out to which MPIO. The ...

  • Page 43

    ... RECOUT0 or RECOUT1, two independent multiplexers, are provided To use the limited pins of the PCM9211 economically, the DIR flag outputs and the GPIO are used at same time within the number of MPIO pins assigned to DIR flags or to GPIO functions. DIR flags or GPIO can be selected for each MPIO zone by using Registers MPASEL[1:0], MPBSEL[2:0], and MPCSEL[2:0] To identify the pins in each MPIO group, the convention * represents ...

  • Page 44

    ... AUXIN1 (ASCKI1/ABCKI1/ALRCKI1/ADIN1) (default) ADC Standalone, clock, and data (ADSCK/ADBCK/ADLRCK/ADDOUT) Sampling frequency calculated result output, SFSOUT[3:0] DIR Flags output or GPIO DIR BCUV output (BFRAME/COUT/UOUT/VOUT) DIT Standalone, clock, and data (TXSCK/TXBCK/TXLRCK/TXDIN) Reserved Reserved Product Folder Link(s): PCM9211 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 45

    ... Table 16. MPO1 Pin MPO1 FUNCTION Hi-Z GPO1, Output data = Logic high level GPO1, Output data = Logic low level VOUT (default) INT0 INT1 CLKST EMPH BPSYNC DTSCD PARITY LOCK XMCKO TXOUT RECOUT0 RECOUT1 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 Submit Documentation Feedback 45 ...

  • Page 46

    ... Description for Signal Name Assigned to MPIO Table 17 through Table 25 list the details of where each of the internal PCM9211 signals can be routed to. For instance, DIR LOCK can be output to any of the MPIO and MPO pins, while SBCK (Secondary Clock Output) can only be brought out through MPIO_A0. SIGNAL NAME ...

  • Page 47

    ... General-purpose output General-purpose output General-purpose output General-purpose input General-purpose input General-purpose input General-purpose input General-purpose output General-purpose output General-purpose output General-purpose output General-purpose input General-purpose input General-purpose input General-purpose input Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 Submit Documentation Feedback 47 ...

  • Page 48

    ... Table 28. MPIO Group C ASSIGNED PIN FUNCTION MPIO_C1 ABCKI1 ADBCK SFSOUT2 (1) (1) DIR Flag / GPIO DIR Flag / GPIO COUT TXBCK Reserved Reserved Product Folder Link(s): PCM9211 www.ti.com MPIO_A2 MPIO_A3 RXIN10 RXIN11 XMCKO INT0 XMCKO INT0 (1) (1) DIR Flag / GPIO MPIO_B2 MPIO_B3 ...

  • Page 49

    ... Data Figure 32. Default Routing Block Diagram By default, the ADC starts clock slave to the crystal that is connected to the PCM9211. The DIR receives data on RXIN2. When the DIR is unlocked, the ADC has priority, and uses the Main port. When the DIR is locked, data from the MAIN PORT are DIR data. ...

  • Page 50

    ... Multi-Channel PCM Routing Function Overview The PCM9211 has a multi-channel PCM routing function (maximum of eight channels) that can route multi-channel PCM signals easily. This function is enabled by using all the MPIOs. MPIO_A and MPIO_C are assigned as multi-channel PCM input ports and clock transition outputs (CLKST). ...

  • Page 51

    ... ADC DATA and the ADC clock source. DSD Input Mode The PCM9211 can also be used to suppress the jitter of the DSCKI signals, typically generated by an HDMI receiver. DSD signals (DBCKI, DSDRI, DSDLI) are routed to the Main Port as DBCKO, DSDRO, and DSDLO, respectively ...

  • Page 52

    ... TXDSD = Enable 6Bh = 14h MOSSRC = DIR MOPSRC = AUXIN1 DESCRIPTIONS 34h = CFh RXSEL = TXOUT 60h = 55h TXSSRC = AUXIN2 TXPSRC = AUXIN2 61h = 14h TXDSD = Enable 6Bh = 14h MOSSRC = DIR MOPSRC = AUXIN1 Product Folder Link(s): PCM9211 www.ti.com Copyright © 2010, Texas Instruments Incorporated ...

  • Page 53

    ... ADC ADC Mode Control AUTO DIR ADC AUXIN0 AUXIN1 Red lines are DSCKO generation paths. Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 RXIN7 SCKO ( DSCKO) DOUT BCK (DBCKO ) MAIN OUTPUT LRCK (DSDRO ) PORT DOUT ( DSDLO) SCKO from DIR BCK from AUXIN 1 ...

  • Page 54

    ... PCM9211 SBAS495 – JUNE 2010 Serial Control Mode The PCM9211 supports two types of control interface, which are set using the MODE pin (pin 27), as defined in Table 33. MODE Tied to DGND Tied to VDD The input state of the MODE pin is only sampled during a power-on reset or external reset event. Therefore, any change after device power on or external reset is ignored ...

  • Page 55

    ... Figure 37. Register Write Operation after the start of the block. However, once ADR 0 DON ’T CARE Figure 38. Register Read Operation Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 ADR ADR “HI -Z ” ...

  • Page 56

    ... The PCM9211 has seven bits for its own slave address. The first five bits (MSB) of the slave address are factory-preset to '10000'. The next two bits of the address byte are selectable bits that can be set by MDO/ADR0 and MS/ADR1. A maximum of four PCM9211s can be connected on the same bus at one time. Each PCM9211 responds when it receives its own slave address ...

  • Page 57

    ... Write Operation The PCM9211 can only function single or multiple accesses. The master sends a PCM9211 slave address with a write bit, a register address, and the data. When undefined registers are accessed, the PCM9211 does not send an acknowledgment. illustrates the write operation. The register address and the write data are 8-bit, MSB-first format. ...

  • Page 58

    ... STANDARD MODE MIN MAX 100 4.7 4.7 4.0 4.7 4.0 250 0 3450 1000 1000 1000 1000 4.0 400 0.2 × 0.1 × n/a Figure 43. Control Interface Timing Product Folder Link(s): PCM9211 www.ti.com Stop t SDA SDA-R P- FAST MODE MIN MAX UNITS 400 kHz 1.3 µs 1.3 µs 0.6 µs 0.6 µs 0.6 µ ...

  • Page 59

    ... C13 0V +3.3V MPIO _ B MPOx PCM Assigned Assigned Audio Functions Functions I/ F Figure 44. Typical Circuit Connection Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 0V COAX Input R3 C10 C12 36 +3.3V VDDRX R4 C11 35 COAX Input RXIN1 34 RST 33 RXIN2 32 RXIN3 ...

  • Page 60

    ... 330 0 0 kHz C Figure 45 Submit Documentation Feedback biased buffering for 2-V input with overvoltage protection. RMS Biased Buffering Example COM Product Folder Link(s): PCM9211 www.ti.com +V +5V Output - V VCOM 0V Copyright © 2010, Texas Instruments Incorporated ...

  • Page 61

    ... TXCS6 TXCS5 TXCS4 R/W TXCS15 TXCS14 TXCS13 TXCS12 R/W TXCS23 TXCS22 TXCS21 TXCS20 R/W TXCS31 TXCS30 TXCS29 TXCS28 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 ERRHZ ERRSEL NPCMHZ NPCMSEL RSV RSV RSV RSV RSV RSV RSV RXVDLY PRTPRO1 PRTPRO0 ERRWT1 ...

  • Page 62

    ... GIOB0DIR R/W RSV RSV RSV R/W GPOB3 GPOB2 GPOB1 GPOB0 R/W RSV RSV RSV R GPIB3 GPIB2 GPIB1 R RSV RSV RSV Product Folder Link(s): PCM9211 www.ti.com TXCS35 TXCS34 TXCS33 TXCS32 TXCS43 TXCS42 TXCS41 TXCS40 AOLRMTE MOLRMTE RSV AODMUT MODMUT N N RSV MOPSRC2 ...

  • Page 63

    ... NPCMSEL: NPCM/INT1 Port Output Source Select 0: NPCM (default) 1: INT1 spacer Copyright © 2010, Texas Instruments Incorporated NOTE (Address: 20h, Write and Read MCHR RSV ERRHZ Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 ERRSEL NPCMHZ NPCMSEL Submit Documentation Feedback 63 ...

  • Page 64

    ... B4 B3 RSV RXFSRNG RSV Register 22h, DIR Initial Settings 2/3 (Address: 22h, Write and Read RSV CLKSTP RSV Product Folder Link(s): PCM9211 www.ti.com RSV RSV RSV RSV RSV RXVDLY Copyright © 2010, Texas Instruments Incorporated ...

  • Page 65

    ... Copyright © 2010, Texas Instruments Incorporated Register 23h, DIR Initial Settings 3/3 (Address: 23h, Write and Read XTIWT1 XTIWT0 PRTPRO1 Range Setting and Mask registers. S Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 PRTPRO0 ERRWT1 ERRWT0 kHz S Submit Documentation Feedback 65 ...

  • Page 66

    ... XTI/1 (24.576 MHz) (default) 01: XTI/2 (12.288 MHz) 10: XTI/4 (6.144 MHz) 11: XTI/8 (3.072 MHz) 66 Submit Documentation Feedback (Address: 24h, Write and Read RSV XMCKEN XMCKDIV1 Product Folder Link(s): PCM9211 www.ti.com XMCKDIV0 RSV RSV Copyright © 2010, Texas Instruments Incorporated ...

  • Page 67

    ... Copyright © 2010, Texas Instruments Incorporated Register 25h, ERROR Cause Setting (Address: 25h, Write and Read EFSCHG EFSLMT ENPCM Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 EVALID EPARITY EUNLOCK Limit Setting Register. S Submit Documentation Feedback ...

  • Page 68

    ... AUNLOCK: PLL Lock Error 0: Not selected 1: Selected (default) 68 Submit Documentation Feedback (Address: 26h, Write and Read RSV AFSLMT ANPCM Product Folder Link(s): PCM9211 www.ti.com AVALID RSV AUNLOCK Limit Setting Register. S Copyright © 2010, Texas Instruments Incorporated ...

  • Page 69

    ... NOMLMT: Receive Nominal Audio limit (default) 1: Limit PCM9211 receives the nominal audio sampling frequencies within ±2%. The nominal audio sampling frequencies are: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz, 176.4 kHz, 192 kHz ...

  • Page 70

    ... DTSCD flag from the MPIO, MPO, and INT pins as DIR Flag outputs. 70 Submit Documentation Feedback Register 28h, Non-PCM Definition (Address: 28h, Write and Read CS1BPLS NPCMP RSV Detection NOTE Product Folder Link(s): PCM9211 www.ti.com DTSCD PAPB CSBIT1 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 71

    ... DTSCD flag from the MPIO, MPO, and INT pins as DIR Flag outputs. Copyright © 2010, Texas Instruments Incorporated (Address: 29h, Write and Read RSV RSV DTS16 NOTE Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 DTS14 DTSPRD1 DTSPRD0 Submit Documentation Feedback 71 ...

  • Page 72

    ... MFSCHG0: Renewal Flag of f Calculator Result S 0: Not masked 1: Masked (default) 72 Submit Documentation Feedback (Address: 2Ah, Write and Read MEMPHF0 MDTSCD0 MCSRNW0 Product Folder Link(s): PCM9211 www.ti.com MPCRNW0 MFSCHG0 RSV Copyright © 2010, Texas Instruments Incorporated ...

  • Page 73

    ... MADLVL1: ADC Input Level Detection Status 0: Not masked 1: Masked (default) Copyright © 2010, Texas Instruments Incorporated (Address: 2Bh, Write and Read MEMPHF1 MDTSCD1 MCSRNW1 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MPCRNW1 MFSCHG1 MADLVL1 Submit Documentation Feedback 73 ...

  • Page 74

    ... Detect renewal When this register is read, the INT0 output is cleared. 74 Submit Documentation Feedback Register 2Ch, INT0 Output Register (Address: 2Ch, Read-Only OEMPHF0 ODTSCD0 OCSRNW0 N/A N/A N/A Product Folder Link(s): PCM9211 www.ti.com OPCRNW0 OFSCHG0 RSV N/A N/A 0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 75

    ... When this register is read, the INT1 output is cleared. Copyright © 2010, Texas Instruments Incorporated Register 2Dh, INT1 Output Register (Address: 2Dh, Read-Only OEMPHF1 ODTSCD1 OCSRNW1 N/A N/A N/A Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 OPCRNW1 OFSCHG1 OADLVL1 N/A N/A N/A Submit Documentation Feedback 75 ...

  • Page 76

    ... B4 B3 RSV ADLVLTH1 ADLVLTH0 Register 2Fh, DIR Output Data Format (Address: 2Fh, Write and Read RSV RSV RSV Product Folder Link(s): PCM9211 www.ti.com INT0P RSV RSV RXFMT2 RXFMT1 RXFMT0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 77

    ... S 101: Reserved 110: Reserved 111: Reserved Copyright © 2010, Texas Instruments Incorporated (Address: 30h, Write and Read RSV PSCKAUTO RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 PSCK2 PSCK1 PSCK0 Submit Documentation Feedback 77 ...

  • Page 78

    ... Submit Documentation Feedback (Address: 31h, Write and Read XSCK1 XSCK0 XBCK1 NOTE Product Folder Link(s): PCM9211 www.ti.com XBCK0 XLRCK1 XLRCK0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 79

    ... LRCK) S 101: Reserved 110: Reserved 111: Reserved spacer Copyright © 2010, Texas Instruments Incorporated (Address: 32h, Write and Read PSBCK1 PSBCK0 RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 PSLRCK2 PSLRCK1 PSLRCK0 Submit Documentation Feedback 79 ...

  • Page 80

    ... XTI/1024 (24 kHz) 100: XTI/2048 (12 kHz) 101: Reserved 110: Reserved 111: Reserved 80 Submit Documentation Feedback (Address: 33h, Write and Read XSBCK1 XSBCK0 RSV Product Folder Link(s): PCM9211 www.ti.com XSLRCK2 XSLRCK1 XSLRCK0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 81

    ... RXIN0 or RXIN1, without use of the built-in COAX amplifier. Copyright © 2010, Texas Instruments Incorporated (Address: 34h, Write and Read RSV RSV RXSEL3 NOTE Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 RXSEL2 RXSEL1 RXSEL0 Submit Documentation Feedback 81 ...

  • Page 82

    ... TXOUT (internal DIT output) MPO0MUT: MPO0 Mute Control 0: Output (default) 1: MUTE (Logic low level) 82 Submit Documentation Feedback (Address: 35h, Write and Read RSV MPO0MUT RO0SEL3 Product Folder Link(s): PCM9211 www.ti.com RO0SEL2 RO0SEL1 RO0SEL0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 83

    ... Write and Read RSV MPO1MUT RO1SEL3 (Address: 37h, Write and Read RSV RSV RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 RO1SEL2 RO1SEL1 RO1SEL0 PFSTGT2 PFSTGT1 PFSTGT0 Submit Documentation Feedback 83 ...

  • Page 84

    ... Calculating and PFSOUT indicates the previous value when no source comes to the port that is selected by Register 37h/PFSTGT. 84 Submit Documentation Feedback (Address: 38h, Read-Only PFSPO1 PFSPO0 PFSOUT3 N/A N/A N/A NOTE Product Folder Link(s): PCM9211 www.ti.com PFSOUT2 PFSOUT1 PFSOUT0 N/A N/A N/A Copyright © 2010, Texas Instruments Incorporated ...

  • Page 85

    ... The other registers do not have clear functions when these are read. To enable these registers, DIR must be powered on (Register 40h/RXDIS = 0). Copyright © 2010, Texas Instruments Incorporated (Address: 39h, Read-Only RSV RSV SESOUT3 SESOUT2 N/A N/A N/A NOTE Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 SESOUT1 SESOUT0 N/A N/A N/A Submit Documentation Feedback 85 ...

  • Page 86

    ... Buffer (Burst Preamble P Output Register Address: 3Ah, Read-Only PC5 PC4 PC3 N/A N/A N/A Address: 3Bh, Read-Only PC13 PC12 PC11 N/A N/A N/A Product Folder Link(s): PCM9211 www.ti.com PC2 PC1 PC0 N/A N/A N PC10 PC9 PC8 N/A N/A N/A /P [15:0] is not C D Copyright © 2010, Texas Instruments Incorporated ...

  • Page 87

    ... Address: 3Dh, Read-Only PD13 PD12 PD11 N/A N/A N/A Register 40h, System Reset Control (Address: 40h, Write and Read ADDIS RXDIS RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 Output Register PD2 PD1 PD0 N/A N/A N PD10 PD9 PD8 N/A N/A N ...

  • Page 88

    ... SCK/BCK/LRCK dividers). Its frequency is set by the register of XSCK[1:0], XBCK[1:0], and XLRCK[1:0].). 88 Submit Documentation Feedback Register 42h, ADC Function Control 1/3 (Address: 42h, Write and Read ADCKOUT ADDTRX7 ADFSLMT Product Folder Link(s): PCM9211 www.ti.com ADCLK2 ADCLK1 ADCLK0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 89

    ... Write and Read ADATTL5 ADATTL4 ADATTL3 (Address: 47h, Write and Read ADATTR5 ADATTR4 ADATTR3 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 ADATTL2 ADATTL1 ADATTL0 ADATTR2 ADATTR1 ADATTR0 Submit Documentation Feedback 89 ...

  • Page 90

    ... Submit Documentation Feedback Register 48h, ADC Function Control 2/3 (Address: 48h, Write and Read ADIFMD1 ADIFMD0 RSV Product Folder Link(s): PCM9211 www.ti.com RSV ADFMT1 ADFMT0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 91

    ... ADC outputs, DOUT. Copyright © 2010, Texas Instruments Incorporated Register 49h, ADC Function Control 3/3 (Address: 49h, Write and Read RSV ADZCDD ADBYP Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 ADPHSE ADMUTR ADMUTL Submit Documentation Feedback 91 ...

  • Page 92

    ... CS Bit19 RXCS29 RXCS28 RXCS27 CS Bit29 CS Bit28 CS Bit27 RXCS37 RXCS36 RXCS35 CS Bit37 CS Bit36 CS Bit35 RXCS45 RXCS44 RXCS43 CS Bit45 CS Bit44 CS Bit43 Product Folder Link(s): PCM9211 www.ti.com RXCS2 RXCS1 RXCS0 CS Bit2 CS Bit1 CS Bit0 RXCS10 RXCS9 RXCS8 CS Bit10 CS Bit9 CS Bit8 RXCS18 RXCS17 RXCS16 ...

  • Page 93

    ... Reserved 111: Reserved Copyright © 2010, Texas Instruments Incorporated Register 60h, DIT Function Control 1/3 (Address: 60h, Write and Read TXSSRC1 TXSSRC0 RSV Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 TXPSRC2 TXPSRC1 TXPSRC0 Submit Documentation Feedback 93 ...

  • Page 94

    ... Submit Documentation Feedback Register 61h, DIT Function Control 2/3 (Address: 61h, Write and Read TXSCK1 TXSCK0 RSV NOTE ), MPIO_B2 for L-ch data, and S Product Folder Link(s): PCM9211 www.ti.com TXDSD TXFMT1 TXFMT0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 95

    ... TXCS29 TXCS28 TXCS27 CS Bit29 CS Bit28 CS Bit27 TXCS37 TXCS36 TXCS35 CS Bit37 CS Bit36 CS Bit35 TXCS45 TXCS44 TXCS43 CS Bit45 CS Bit44 CS Bit43 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 RSV RSV RSV TXCS2 TXCS1 TXCS0 CS Bit2 CS Bit1 CS Bit0 TXCS10 ...

  • Page 96

    ... Mute (the affected signals are selected by Register 6Ah, MOLRMTEN) Data mutes are done in synchronization with a LRCK edge. 96 Submit Documentation Feedback (Address: 6Ah, Write and Read RSV RSV AOLRMTEN Product Folder Link(s): PCM9211 www.ti.com AODMUT MOLRMTEN MODMUT Copyright © 2010, Texas Instruments Incorporated ...

  • Page 97

    ... This source control register is divided into two parts (MOSSRC and MOPSRC). This architecture allows some additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI receiver S/PDIF output is connected with the PCM9211 S/PDIF input, and the HDMI receiver I (BCK/LRCK/DATA) are connected with the PCM9211 PCM input port. ...

  • Page 98

    ... This source control register is divided into two parts (MOSSRC and MOPSRC). This design allows some additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI receiver S/PDIF output is connected to the PCM9211 S/PDIF input, and the HDMI receiver I (BCK/LRCK/DATA) are connected with the PCM9211 PCM input port. ...

  • Page 99

    ... DOUTHZ: Main Output Port, DOUT Hi-Z Control 0: Output (default) 1: Hi-Z Copyright © 2010, Texas Instruments Incorporated (Address: 6Dh, Write and Read MPB1HZ MPB0HZ SCKOHZ Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 BCKHZ LRCKHZ DOUTHZ Submit Documentation Feedback 99 ...

  • Page 100

    ... In multi-channel PCM mode, the MCHR and MPAxHz registers (20h) must be set to '0' to get the outputs from the main port. 100 Submit Documentation Feedback (Address: 6Eh, Write and Read MPC1HZ MPC0HZ MPA3HZ NOTE Product Folder Link(s): PCM9211 www.ti.com MPA2HZ MPA1HZ MPA0HZ Copyright © 2010, Texas Instruments Incorporated ...

  • Page 101

    ... DIT Standalone Operation, Clock, and Data I/O, TXSCK/TXBCK/TXLRCK/TXDIN 110: Reserved 111: Reserved Copyright © 2010, Texas Instruments Incorporated (Address: 6Fh, Write and Read MPBSEL2 MPBSEL1 MPBSEL0 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MPCSEL2 MPCSEL1 MPCSEL0 Submit Documentation Feedback 101 ...

  • Page 102

    ... MPA0SEL: MPIO_A0 Pin Function, DIR Flags or GPIO Select 0: DIR Flags, set by MPA0FLG[3:0] (default) 1: GPIO, set by GIOA0DIR/GPOA0/GPIA0 102 Submit Documentation Feedback (Address: 70h, Write and Read MCHRSRC1 MCHRSRC0 MPA3SEL Product Folder Link(s): PCM9211 www.ti.com MPA2SEL MPA1SEL MPA0SEL Copyright © 2010, Texas Instruments Incorporated ...

  • Page 103

    ... DIR Flags, set by MPC0FLG[3:0] (default) 1: GPIO, set by GIOC0DIR/GPOC0/GPIC0 Copyright © 2010, Texas Instruments Incorporated (Address: 71h, Write and Read MPB1SEL MPB0SEL MPC3SEL Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MPC2SEL MPC1SEL MPC0SEL Submit Documentation Feedback 103 ...

  • Page 104

    ... These register settings are effective only at MPASEL[1:0] = '11', MPA3SEL = '0', and MPA2SEL = '0'. 104 Submit Documentation Feedback (Address: 72h, Write and Read MPA1FLG1 MPA1FLG0 MPA0FLG3 Product Folder Link(s): PCM9211 www.ti.com MPA0FLG2 MPA0FLG1 MPA0FLG0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 105

    ... These register settings are effective only at MPASEL[1:0] = '11', MPA3SEL = '0', and MPA2SEL = '0'. Copyright © 2010, Texas Instruments Incorporated (Address: 73h, Write and Read MPA3FLG1 MPA3FLG0 MPA2FLG3 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MPA2FLG2 MPA2FLG1 MPA2FLG0 Submit Documentation Feedback 105 ...

  • Page 106

    ... These register settings are effective only at MPBSEL[2:0] = '011', MPB1SEL = '0', and MPB0SEL = '0'. 106 Submit Documentation Feedback (Address: 74h, Write and Read MPB1FLG1 MPB1FLG0 MPB0FLG3 Product Folder Link(s): PCM9211 www.ti.com MPB0FLG2 MPB0FLG1 MPB0FLG0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 107

    ... These register settings are effective only at MPBSEL[2:0] = '011', MPB3SEL = '0', and MPB2SEL = '0'. Copyright © 2010, Texas Instruments Incorporated (Address: 75h, Write and Read MPB3FLG1 MPB3FLG0 MPB2FLG3 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MPB2FLG2 MPB2FLG1 MPB2FLG0 Submit Documentation Feedback 107 ...

  • Page 108

    ... These register settings are effective only at MPCSEL[2:0] = '011', MPC1SEL = '0', and MPC0SEL = '0'. 108 Submit Documentation Feedback (Address: 76h, Write and Read MPC1FLG1 MPC1FLG0 MPC0FLG3 Product Folder Link(s): PCM9211 www.ti.com MPC0FLG2 MPC0FLG1 MPC0FLG0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 109

    ... These register settings are effective only at MPCSEL[2:0] = '011', MPC3SEL = '0', and MPC2SEL = '0'. Copyright © 2010, Texas Instruments Incorporated (Address: 77h, Write and Read MPC3FLG1 MPC3FLG0 MPC2FLG3 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 MPC2FLG2 MPC2FLG1 MPC2FLG0 Submit Documentation Feedback 109 ...

  • Page 110

    ... LOCK 1100: XMCKO 1101: TXOUT (default) 1110: RECOUT0 1111: RECOUT1 110 Submit Documentation Feedback (Address: 78h, Write and Read MPO1SEL1 MPO1SEL0 MPO0SEL3 Product Folder Link(s): PCM9211 www.ti.com MPO0SEL2 MPO0SEL1 MPO0SEL0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 111

    ... These registers are effective only at MPIO_A and MPIO_B assigned as GPIO. I/O direction setting is available by pin. Copyright © 2010, Texas Instruments Incorporated (Address: 79h, Write and Read GIOB1DIR GIOB0DIR GIOA3DIR Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 GIOA2DIR GIOA1DIR GIOA0DIR Submit Documentation Feedback 111 ...

  • Page 112

    ... These registers are effective only at MPIO_C assigned as GPIO. I/O direction setting is available by pin. 112 Submit Documentation Feedback (Address: 7Ah, Write and Read RSV RSV GIOC3DIR Product Folder Link(s): PCM9211 www.ti.com GIOC2DIR GIOC1DIR GIOC0DIR Copyright © 2010, Texas Instruments Incorporated ...

  • Page 113

    ... These registers are effective only as GPIOs are assigned to output. Copyright © 2010, Texas Instruments Incorporated (Address: 7Bh, Write and Read GPOB1 GPOB0 GPOA3 Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 GPOA2 GPOA1 GPOA0 Submit Documentation Feedback 113 ...

  • Page 114

    ... Output high level These registers are effective only as GPIOs are assigned to output. 114 Submit Documentation Feedback (Address: 7Ch, Write and Read RSV RSV GPOC3 Product Folder Link(s): PCM9211 www.ti.com GPOC2 GPOC1 GPOC0 Copyright © 2010, Texas Instruments Incorporated ...

  • Page 115

    ... GPIA0: MPIO_A0 Pin, GPIO Input Data 0: Detect low level 1: Detect high level Copyright © 2010, Texas Instruments Incorporated (Address: 7Dh, Read-Only GPIB1 GPIB0 GPIA3 N/A N/A N/A Product Folder Link(s): PCM9211 PCM9211 SBAS495 – JUNE 2010 GPIA2 GPIA1 GPIA0 N/A N/A N/A Submit Documentation Feedback 115 ...

  • Page 116

    ... Detect high level GPIC0: MPIO_C0 Pin, GPIO Input Data 0: Detect low level 1: Detect high level 116 Submit Documentation Feedback (Address: 7Eh, Read-Only RSV RSV GPIC3 N/A N/A N/A Product Folder Link(s): PCM9211 www.ti.com GPIC2 GPIC1 GPIC0 N/A N/A N/A Copyright © 2010, Texas Instruments Incorporated ...

  • Page 117

    ... Orderable Device (1) Package Type Package Status PCM9211PT ACTIVE LQFP PCM9211PTR ACTIVE LQFP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 118

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing PCM9211PTR LQFP PT PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 1000 330.0 16.4 9.6 Pack Materials-Page 1 23-Jul-2010 Pin1 (mm) (mm) (mm) (mm) Quadrant 9.6 1.9 12.0 16.0 Q2 ...

  • Page 119

    ... Device Package Type PCM9211PTR LQFP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 1000 Pack Materials-Page 2 23-Jul-2010 Width (mm) Height (mm) 346.0 346.0 33.0 ...

  • Page 120

    PT (S-PQFP-G48) 0, 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 1,45 1,35 1,60 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 121

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...