The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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Additional ADC Functions
The onboard ADC has some additional functions. Control of these functions is done using several registers
(Register 40h through Register 49h).
Each ADC channel has a digital attenuator function. The level of attenuation can be set from 20 dB to –100 dB in
0.5-dB steps, and also set to infinite attenuation (mute). By default, the digital gain/attenuation is moved 0.5-dB
steps closer from its current level to its new setting only when the sampled output crosses zero (zero crossing).
Changing gain or attenuation at zero crossing points in the audio minimizes zipper noise.
If zero crossing is disabled, then the gain steps ±0.5 dB towards its target every 8/f
modified using the ADZCDD register. If zero crossing is not detected for 512/f
significant dc bias on the signal), then the level change is done on every samples (1/f
detected again.
If updated volume change instructions are received during a volume change, they will be ignored until the current
change is complete.
The attenuation level for each channel can be set individually using the following formula:
Attenuation Level (dB) = 0.5 ● (AT1x[7:0]
For ADATTL[7:0]
= 0 through 14, attenuation is set to infinite attenuation (mute).
DEC
For ADATTR[7:0]
= 0 through 14, attenuation is set to infinite attenuation (mute).
DEC
ADC: Power Down and Power Up
If synchronization is maintained among SCKI, BCK, and LRCK, the DOUT from the ADC is enabled and a
fade-in begins t
= 2048/f
ADCDLY1
S
corresponding to V
L and V
R after t
IN
IN
maintained, the internal reset is not released, and the ADC is held in reset. After resynchronization, the ADC
begins its fade-in operation after internal initialization and an initial delay. During fade-in (t
fade-out (t
), SCKI, BCK, and LRCK must be provided.
ADCDLY2
power up and power down.
SCK
BCK
LRCK
ADDIS
Internal
Normal Operation
Reset
DOUT
Figure 14. ADC Output at Power Up and Power Down
Copyright © 2010, Texas Instruments Incorporated
– 215), where AT1x[7:0]
DEC
after the internal reset is released. DOUT then starts to output data
= 1936/f
from the start of fade-in. If synchronization is not
ADCDLY2
S
Figure 14
Synchronous Clocks
2048/f min
S
1024 SCKIx
power down
t
ADCDLY2
1936/f
S
ZERO
Fade Out
Product Folder Link(s):
PCM9211
PCM9211
SBAS495 – JUNE 2010
. Zero crossing detection is
S
(for example, if there is a
S
) until zero crossing is
S
= 0 through 255
DEC
+ t
ADCDLY1
ADCDLY2
illustrates the ADC output sequence at
Synchronous Clocks
Normal Operation
t
t
ADCDLY2
ADCDLY1
2048/f
1936/f
S
S
Fade In
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) and
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