The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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In master mode, BCK and LRCK are output from the ADC of PCM9211. BCK and LRCK are generated by the
internal ADC from SCKI, and BCK is fixed as 64f
timing specification is shown in
Figure
t
t
BCH
BC L
BCK
(OUTPUT)
t
BC Y
LRCK
(OUTPUT)
DOUT
SYMBOL
t
BCK cycle time
BCY
t
BCK high time
BCH
t
BCK low time
BCL
t
LRCK delay time to BCK falling edge
LRD
t
DOUT delay time from BCK falling edge
DOD
Note:
Load capacitance of output is 20 pF. This timing requirement is applied when ADC clock source (Register
42h/ADCLK) is AUXIN0, AUXIN1 or AUXIN2. This specification is applied for SCK with a frequency less than 25 MHz.
Figure 16. Audio Data Interface Timing (Master Mode: BCK and LRCK Work as Outputs)
Audio Interface Format
The ADC of the PCM9211 supports the following interface formats in both slave and master modes:
2
24-bit I
S format
24-bit Left-Justified format
24-bit Right-Justified format
16-bit Right-Justified format
All formats are provided twos complement, MSB first. ADC interface formats are set using Register 48h.
ADC and Synchronization with Other Clocks
The PCM9211 operates under the system clock (SCKI) and the audio sampling clock (LRCK). The PCM9211
does not require a specific phase relationship between audio interface clocks (LRCK, BCK) and the system clock
(SCKI), but does require the synchronization in the frequency of LRCK, BCK and SCKI. This requirement allows
SCKI to be provided elsewhere than from LRCK and BCK.
LRCK and BCK require synchronization at all times.
If the relationship between SCKI and LRCK changes more than ±6 BCKs as a result of jitter, a frequency
change, and so forth, the internal operation of the ADC stops within 2/f
codes until resynchronization between SCKI and LRCK and BCK is completed. Real data begin to be generated
a period of t
later.
ADCDLY3
Changes or drift less than ±5 BCKs do not cause any issues with the device.
output when synchronization is lost.
The ADC output, DOUT, maintains its previous state if the system clock stops.
Copyright © 2010, Texas Instruments Incorporated
. DOUT changes on the falling edge of BCK. The detailed
S
16.
t
LRD
t
DOD
DESCRIPTION
Product Folder Link(s):
PCM9211
PCM9211
SBAS495 – JUNE 2010
0.5 V
DD
0.5 V
DD
0.5 V
DD
MIN
TYP
MAX
UNITS
1/64f
S
0.4 t
0.5 t
0.6 t
BCY
BCY
BCY
0.4 t
0.5 t
0.6 t
BCY
BCY
BCY
0
30
ns
0
30
ns
, and the digital output will be ZERO
S
Figure 17
shows the ADC digital
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