The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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PLL Clock Source (Built-in PLL and VCO) Details
The PCM9211 an has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock
from the S/PDIF input signal.
The VCO-derived clock is identified as the PLL clock source.
When locked, the onboard PLL generates a system clock that synchronizes with the input biphase signal. When
unlocked, the PLL generates its own free-run clock (from the VCO).
The generated system clocks from the PLL can be set to fixed multiples of the input S/PDIF frequency. Register
30h/PSCK[2:0] can configure the output clock to 128f
The PCM9211 also has an automatic default output rate that is calculated based on the incoming S/PDIF
frequency. This calculation and rate are controlled by Register 30h/PSCKAUTO. In its default mode, the SCK
dividing ratio is configured according to these parameters:
512f
: 54 kHz and below.
S
256f
: 54 kHz to 108 kHz
S
128f
: 108 kHz and above (or unlocked)
S
PSCKAUTO takes priority over any settings in PSCK[2:0]. PSCK[2:0] only becomes relevant in the system when
the PSCKAUTO Register is set to '0'.
The PCM9211 can decode S/PDIF input signals between sampling frequencies of 7 kHz and 216 kHz for all
PSCK[2:0] settings. The relationship between the output clock (SCKO, BCKO, LRCKO) at the PLL source and
PSCK[2:0] selection is shown in
Table
Table 4. SCKO, BCKO and LRCKO Frequency Set by PSCK[2:0]
OUTPUT CLOCK AT PLL SOURCE
SCKO
BCKO
128f
64f
S
256f
64f
S
(1)
512f
64f
S
(1) 512f
SCK is only supported at 108 kHz or lower sampling frequency of incoming biphase signal.
S
In PLL mode, the output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock.
The relationship between the sampling frequencies (f
BCKO, and SCKO are shown in
Table
Table 5. Output Clock Frequency at PLL Lock State
LRCK
f
S
8 kHz
11.025 kHz
0.7056 MHz
12 kHz
16 kHz
22.05 kHz
1.4112 MHz
24 kHz
32 kHz
44.1 kHz
2.8224 MHz
48 kHz
64 kHz
88.2 kHz
5.6448 MHz
96 kHz
128 kHz
176.4 kHz
11.2896 MHz
192 kHz
12.288 MHz
Copyright © 2010, Texas Instruments Incorporated
, 256f
or 512f
.
S
S
S
4.
PSCK[2:0] SETTING
LRCKO
PSCK2
f
0
S
S
f
0
S
S
f
1
S
S
) of the input S/PDIF signal and the frequency of LRCKO,
S
5.
BCK
SCK (Depends on PSCK[2:0] Setting)
64f
128f
S
S
0.512 MHz
1.024MHz
2.048 MHz
1.4112 MHz
2.8224 MHz
0.768 MHz
1.536 MHz
3.072 MHz
1.024 MHz
2.048 MHz
4.096 MHz
2.8224 MHz
5.6448 MHz
1.536 MHz
3.072 MHz
6.144 MHz
2.048 MHz
4.096 MHz
8.192 MHz
5.6448 MHz
11.2896 MHz
3.072 MHz
6.144 MHz
12.288 MHz
4.096 MHz
8.192 MHz
16.384 MHz
11.2896 MHz
22.5792 MHz
6.144 MHz
12.288 MHz
24.576 MHz
8.192 MHz
16.384 MHz
32.768 MHz
22.5792 MHz
45.1584 MHz
24.576 MHz
49.152 MHz
Product Folder Link(s):
PCM9211
PCM9211
SBAS495 – JUNE 2010
PSCK1
PSCK0
0
0
1
0
0
0
256f
512f
S
S
4.096 MHz
5.6448 MHz
6.144 MHz
8.192 MHz
11.2896 MHz
12.288 MHz
16.384 MHz
22.5792 MHz
24.576 MHz
32.768 MHz
45.1584 MHz
49.152 MHz
N/A
N/A
N/A
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