The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Page 33/121

Download datasheet (2Mb)Embed
PrevNext
www.ti.com
Upon receipt of an interrupt source (such as f
of AND (&) with an inverted mask [Register 2Ah (INT0) and Register 2Bh (INT1)], then perform an eight-way OR
of the data. If the output is '1', then INTx is set to '1', which can be used to trigger an interrupt in the host DSP.
The host can then poll the INTx register to determine the interrupt source.
device uses to mask the DIR interrupts from the INTx register.
Once the register is read, each of the bits in the register (INT0 and INT1) are cleared. If the signal is routed to
ERR/INT0 or NPCM/INT1, the output pin is also cleared.
By default, the mask registers are set to mask all inputs; that is, all inputs are rejected, in which case no interrupt
can be seen on the output until the mask is changed.
A block diagram for the error output and interrupt output is shown in
INT0/1
Mask
INT0/1
Register
f Calculator
S
Complete
DIR
‘1’
Figure 28. Error Output and Interrupt Output Block Diagram
Copyright © 2010, Texas Instruments Incorporated
Calculator Complete), INT0 or INT1 performs a bitwise evaluation
S
Interrupt Source
To INTx
Mask Bit
Figure 27. DIR Interrupt Mask Logic
Figure
Product Folder Link(s):
PCM9211
PCM9211
SBAS495 – JUNE 2010
Figure 27
shows the logic that the
28.
Hi-Z
ERR/INT0
External Pin
Hi-Z
NPCM/INT1
External Pin
Submit Documentation Feedback
33