The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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Page 46/121

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PCM9211
SBAS495 – JUNE 2010
MPIO Description
Description for Signal Name Assigned to MPIO
Table 17
through
Table 25
list the details of where each of the internal PCM9211 signals can be routed to. For
instance, DIR LOCK can be output to any of the MPIO and MPO pins, while SBCK (Secondary Clock Output)
can only be brought out through MPIO_A0.
SIGNAL NAME
MPIO GROUP / PIN
CLKST
All MPIOs, MPO0/1
INT0
All MPIOs, MPO0/1
INT1
All MPIOs, MPO0/1
EMPH
All MPIOs, MPO0/1
BPSYNC
All MPIOs, MPO0/1
DTSCD
All MPIOs, MPO0/1
PARITY
All MPIOs, MPO0/1
LOCK
All MPIOs, MPO0/1
Table 18. DIR B Frame, Channel Status, User Data, Validity Flag Output
SIGNAL NAME
MPIO GROUP / PIN
BFRAME
All MPIOs, MPO0/1
COUT
All MPIOs
UOUT
All MPIOs
VOUT
All MPIOs
Table 19. DIR Calculated Sampling Frequency Output
SIGNAL NAME
MPIO GROUP / PIN
SFSOUT0
All MPIOs
SFSOUT1
All MPIOs
SFSOUT2
All MPIOs
SFSOUT3
All MPIOs
SIGNAL NAME
MPIO GROUP / PIN
RXIN8
MPIO_A0
RXIN9
MPIO_A1
RXIN10
MPIO_A2
RXIN11
MPIO_A3
SIGNAL NAME
MPIO GROUP / PIN
RECOUT0
MPO0/1
RECOUT1
MPO0/1
TXOUT
MPO0/1
SIGNAL NAME
MPIO GROUP / PIN
SBCK
MPIO_A0
SLRCK
MPIO_A1
XMCKO
MPIO_A2, MPO0/1
46
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Table 17. DIR Flags Output
DESCRIPTION
Clock transient status signal output
Interrupt system 0, Interrupt event detection output
Interrupt system 1, Interrupt event detection output
Channel status, emphasis detection output
Burst preamble sync signal output
DTS-CD/LD detection output
Biphase parity error detection output
PLL lock detection output
DESCRIPTION
B frame output
Channel status data
User data
Validity flag
DESCRIPTION
Calculated f
, decoded output, bit0
S
Calculated f
, decoded output, bit1
S
Calculated f
, decoded output, bit2
S
Calculated f
, decoded output, bit3
S
Table 20. Biphase Input
DESCRIPTION
Biphase signal input 8
Biphase signal input 9
Biphase signal input 10
Biphase signal input 11
Table 21. Biphase Output
DESCRIPTION
Independent biphase selector 0, output0
Independent biphase selector 1, output1
Built-in DIT, biphase output
Table 22. AUX Clocks Output
DESCRIPTION
Secondary bit clock output
Secondary LR clock output
XTI pin input clock buffered output
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PCM9211
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Copyright © 2010, Texas Instruments Incorporated