The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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Output Source Selection
The output source for Multi-Channel PCM Output (the Main output port and MPIO_B) is selected by a register.
Table 29
describes the relationship between the output source and the register (MCHRSRC) setting.
Table 29. Multi-Channel PCM Output Source and Register Setting
MULTI-CHANNEL MODE
OUTPUT SOURCE SELECT
CLOCK SOURCE
DOUT
MDOUT0
MDOUT1
MDOUT2
MDOUT3
(1) The Main OUT data source is discussed in the
recovered clock and data, or the ADC DATA and the ADC clock source.
DSD Input Mode
The PCM9211 can also be used to suppress the jitter of the DSCKI signals, typically generated by an HDMI
receiver. DSD signals (DBCKI, DSDRI, DSDLI) are routed to the Main Port as DBCKO, DSDRO, and DSDLO,
respectively.
The DIT works with DSCKI for SCK, DBCKI for BCK, internally-created LRCK, DBCKI divided by 64, and '0' data
for DIN.
MOLRMTEN (Register 6Ah) can be used to mute/unmute DSDRO from the LRCK port. When MOLRMTEN is set
to '1', mute/unmute of DSDRO from LRCK is available by MODMUT = 1/0.
Table 30
summarizes the DSD input mode configuration.
SIGNAL NAME
MPIO GROUP / PIN
MPIO_C0 or
DSCKI
MPIO_B0
MPIO_C1 or
DBCKI
MPIO_B1
MPIO_C2 or
DSDRI
MPIO_B2
MPIO_C3 or
DSDLI
MPIO_B3
DSCKO
SCKO
DBCKO
BCK
DSDRO
LRCK
DSDLO
DOUT
DBCK
DSDRI
DSDLI
Copyright © 2010, Texas Instruments Incorporated
MCHRSRC
'00' or '10'
(1)
MAIN OUT
(1)
MAIN OUT
(1)
MAIN OUT
Logic low
Logic low
Logic low
DIR
section of this data sheet. It can either be the DIR
Figure 34
illustrates the DSD format.
Table 30. DSD Input Mode Summary
DESCRIPTION
SCK input (256f
)
S
DBCK input for DSD format (64f
)
S
R-channel DSD data input for DSD format
L-channel DSD data input for DSD format
SCK output generated by DIR from DIT output
DBCK output for DSD format (the same signal as DBCKI)
R-channel DSD data output for DSD format (the same signal as DSDRI)
L-channel DSD data output for DSD format(the same signal as DSDLI)
1
2
3
62
63
64
1
2
3
62
63
64
Figure 34. DSD Format
Product Folder Link(s):
PCM9211
PCM9211
SBAS495 – JUNE 2010
'01' or '11'
MULTI-CH INPUT
MDIN0
MDIN0
MDIN1
MDIN2
MDIN3
1
2
3
1
2
3
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