The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
Page 6/121

Download datasheet (2Mb)Embed
PrevNext
PCM9211
SBAS495 – JUNE 2010
ELECTRICAL CHARACTERISTICS: Digital Audio I/F Receiver (DIR)
All specifications at T
= +25°C, V
= V
A
CC
PARAMETER
DIR, COAXIAL INPUT AMPLIFIER (RXIN0 and RXIN1)
Input resistance
Input voltage
Input hysteresis
Input sampling frequency
DIR, BIPHASE SIGNAL INPUT and PLL
Normal mode
Input biphase sampling
frequency range
Wide mode
Input sampling frequency
IEC60958-3 (2003-01)
accuracy
Jitter tolerance
IEC60958-3 (2003-01)
From biphase signal detection to error out
(1)
PLL lock up time
release (ERROR = L)
DIR, RECOVERED CLOCK and DATA
Serial audio data width
128f
S
System clock frequency
256f
S
512f
S
Bit clock frequency
64f
S
LR clock frequency
f
S
f
= 48 kHz, SCKO = 256f
S
System clock jitter
period jitter
System clock duty cycle
50% reference
DIT
Output biphase sampling
frequency
128f
S
Input system clock frequency
256f
S
512f
S
Input bit clock frequency
64f
S
Input LR clock frequency
f
S
OSCILLATOR CIRCUIT, XTI and XMCKO CLOCK
XTI source clock frequency
Frequency accuracy
XTI input clock duty cycle
XMCKO frequency
XMCKO output duty cycle
50% reference
PCM OUTPUT PORT (SCKO, BCK, LRCK, DOUT)
System clock frequency
128f
S
Bit clock output frequency
64f
S
LR clock output frequency
f
S
ROUTING
System clock frequency
128f
S
Bit clock output Frequency
64f
S
LR clock output frequency
f
S
(1) PLL lock-up time varies with ERROR release wait time setting (Register 23h/ERRWT). Therefore, lock-up time in this table shows the
value at ERRWT = 11 as the shortest time setting.
6
Submit Documentation Feedback
= V
= 3.3 V, and V
= 5 V, unless otherwise noted.
DD
DDRX
CCAD
TEST CONDITIONS
, measured
S
/ 256f
/ 512f
S
S
/ 256f
/ 512f
S
S
Product Folder Link(s):
PCM9211
www.ti.com
PCM9211
MIN
TYP
MAX
UNIT
20
0.2
V
PP
50
mV
7
216
kHz
28
108
kHz
7
216
kHz
Level III (±12.5%)
IEC60958-3
100
ms
16
24
Bits
0.896
27.648
MHz
1.792
55.296
MHz
3.584
55.296
MHz
0.448
13.824
MHz
7
216
kHz
50
100
ps, rms
±5
±5
%
7
216
kHz
0.896
27.648
MHz
1.792
55.296
MHz
3.584
55.296
MHz
0.448
13.824
MHz
7
216
kHz
24.576
MHz
–100
100
ppm
45
55
%
24.576
MHz
±5
±5
%
0.896
55.296
MHz
0.448
13.824
MHz
7
216
kHz
0.896
55.296
MHz
0.448
13.824
MHz
7
216
kHz
Copyright © 2010, Texas Instruments Incorporated