The PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders

PCM9211

Manufacturer Part NumberPCM9211
DescriptionThe PCM9211 is a complete analog and digital front-end for today's multimedia players and recorders
ManufacturerTexas Instruments
PCM9211 datasheet
 


Specifications of PCM9211

Jitter(ps)50Sampling Rate(max)(khz)216
Power Supply(v)4.5-5.5 for Analog ,2.9-3.6 for DIXAdc Resolution(bits)24
Adc Sample Rate (ksps)96Control ModeSPI, I2C, Hardware
InputsPCM,S/PDIF, ADCOutputPCM,S/PDIF
Operating Temperature Range(c)-40 to 85Pin/package48LQFP
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Page 64/121

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PCM9211
SBAS495 – JUNE 2010
DATA
B7
B6
Reg Name
RSV
RSV
Default Value
0
0
Memo
RXFSRNG: DIR Receivable Incoming Biphase Sampling Frequency Range Setting
0: Wide Mode (7 kHz to 216 kHz) (default)
1: Normal Mode (28 kHz to 108 kHz)
spacer
DATA
B7
B6
Reg Name
RSV
CLKSTCON
Default Value
0
0
Memo
CLKSTCON: CLKST Output Condition Setting
0: Only PLL Lock status change (default)
1: All events where the Main port output clock condition changes, as well as these cases:
1. MOSSRC/MOPSRC Register is updated to ADC, AUXIN0, AUXIN1, or AUXIN2
2. DIR and ADC are switched by DIR status when MOSSRC = 000(AUTO) and MOPSRC =
000(AUTO)
3. Main port sampling frequency changes when PFSTGT = 101(Main output port)
NOTES:
CLKST never outputs when updating MOSSRC and MOPSRC to AUTO or DIR.
OSCAUTO must be '0' when CLKST is used because CLKST is generated by frequency counting of
built-in oscillator circuit.
To output CLKST, MOSSRC and MOPSRC are set simultaneously.
CLKSTP: CLKST Polarity Setting
0: Active low (default)
1: Active high
RXVDLY: VOUT Delay Setting
0: VOUT is active immediately after validity flag is detected
1: VOUT is active after synchronization with DOUT data (default)
64
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Register 21h, DIR Initial Settings 1/3
(Address: 21h, Write and Read)
B5
B4
B3
RSV
RXFSRNG
RSV
0
0
0
Register 22h, DIR Initial Settings 2/3
(Address: 22h, Write and Read)
B5
B4
B3
RSV
CLKSTP
RSV
0
0
0
Product Folder Link(s):
PCM9211
www.ti.com
B2
B1
B0
RSV
RSV
RSV
0
0
0
B2
B1
B0
RSV
RSV
RXVDLY
0
0
1
Copyright © 2010, Texas Instruments Incorporated