TSC2102

... The TSC2102 also features a high-performance audio DAC with 16, 20, 24, or 32-bit stereo playback functionality ksps. The stereo output drivers on the TSC2102 can be programmed for headphone drive or line-level drive, and support capless as well as ac-coupled output  ...

... VGND 28 DRVDD 29 HPR 30 RESET 31 LRCK 32 PWD www.ti.com TRANSPORT MEDIA TSC2102IDA Rails TSC2102IDAR Tape and Reel DESCRIPTION I Battery monitor input 1 I/O Reference voltage I Analog ground I/O Y− position input and driver I/O X− position input and driver I/O Y+ position input and driver I/O X+ position input and driver ...

... ADC ADC Battery conversion not selected Programmable: 8-, 10-,12-bits 12-bit resolution Gain error is calculated with the effect of internal reference variation removed. TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 UNITS −0 3.9 V −0 3.9 V −0 3.9 V −0 2.5 V −0 IOVDD + 0.3 V − ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) At +25°C, AVDD,DRVDD,IOVDD = 3.3 V, DVDD = 1.8 V, Int. V ref = 2 (Audio kHz, unless otherwise noted (continued) PARAMETER DAC LINE OUTPUT (16−W driver bypassed) Full scale output voltage (0 dB) Output common mode SNR ...

... VGND off, PLL off, no signal IAVDD + IDRVDD, headphone driver and VGND on, PLL off, no signal 48 ksps, PLL off, no signal IDRVDD IDVDD Hardware power down. All digital inputs IOVDD. TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 MIN TYP MAX UNITS 2.7 3 ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 FUNCTIONAL BLOCK DIAGRAM DRVDD DRVSS Headphone Driver HPR Headphone Driver HPL DAC CM VGND AUX X+ Touch Y+ Panel X− Drivers Y− Battery VBAT1 Monitor Battery VBAT2 Monitor Temperature Measurement VREF 6 AVDD AVSS DVDD DVSS ...

... Fall time (1) These parameters are based on characterization and are not tested in production. t Lag BIT LSB OUT BIT LSB IN PARAMETER TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 dis MIN MAX UNITS ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 AUDIO INTERFACE TIMING DIAGRAMS LRCK BCLK DIN Figure 1. I2S/LJF/RJF Timing in Master Mode TYPICAL TIMING REQUIREMENTS All specifications at 25°C, IOVDD = 3.3 V, DVDD = 1 (WS) LRCK delay t s (DI) DIN setup t h (DI) DIN hold t r Rise time ...

... Fall time (1) These parameters are based on characterization and are not tested in production (WS) PARAMETER t h (WS (WS) Figure 4. DSP Timing in Slave Mode PARAMETER TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 t h (DI (DI) MIN MAX UNITS ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 1.5 1 0.5 0 −0.5 −1 −1.5 0 Figure 5. SAR INL (T 1 0.5 0 −0.5 −1 0 Figure 6. SAR DNL (T 10 TYPICAL CHARACTERISTICS 500 1000 1500 2000 2500 3000 3500 CODE = 255C, Internal Ref = 2 bit, AVDD = 3 500 ...

... Figure 8. DAC FFT Plot ( Sampling Rate (ksps) = 255C, External Ref, Host Controlled AUX A Conversion, AVDD = 3.3 V) 5000 10000 15000 20000 Hz = 255C, 48 ksps, 0 dB, 1 kHz Input, AVDD = 3 TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 kW ...

... Communication with the TSC2102 is via standard SPI serial interface. This interface requires that the slave select signal be driven low to communicate with the TSC2102. Data is then shifted into or out of the TSC2102 under control of the host microprocessor, which also provides the serial data clock. Control of the TSC2102 and its functions is accomplished by writing to different registers in the TSC2102 ...

... X and Y coordinates to the associated processor. Measuring touch pressure (Z) can also be done with the TSC2102. To determine pen or finger touch, the pressure of the touch needs to be determined. Generally not necessary to have very high performance for this test; therefore, the 8-bit resolution mode is recommended (however, calculations are shown with the 12-bit resolution mode) ...

... This is referred to as the panel voltage stabilization time, and is used in some of the modes available in the TSC2102. In other modes, the TSC2102 can be commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the command is issued to perform a conversion ...

... PINTDAV DATAV X+ X− Y+ Y− VBAT2 VBAT1 AUX AVSS Figure 12. Simplified Diagram of the Analog Input Section SLAS379A− APRIL 2003 − REVISED JUNE 2004 AVDD VREF TSC2102 VREF REFP IN+ CONVERTER IN− REFM 15 ...

... The TSC2102 output data is in unsigned binary format and can be read from the registers over the SPI interface. Reference The TSC2102 has an internal voltage reference that can be set to 1. 2.5 V through the reference control register. The internal reference voltage must only be used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs ...

... In modes where the TSC2102 needs to detect if the screen is still touched (for example, when doing a PINTDAV initiated X, Y, and Z conversion), the TSC2102 must reset the drivers so that the 50-k resistor is connected. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs causes a long delay time, and may prevent the detection from occurring correctly ...

... Conversion Controlled by TSC2102 Initiated at Touch Detect In this mode, the TSC2102 detects when the touch panel is touched and causes the PINTDAV line to go low. At the same time, the TSC2102 starts up its internal clock. Assuming the part was configured to convert XY coordinates, it then turns on the Y drivers, and after a programmed panel voltage stabilization time, powers up the ADC and converts the Y coordinate. If averaging is selected, several conversions may take place ...

... Temperature Measurement In some applications, such as battery recharging, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2102 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (V temperature can be predicted in applications by knowing the 25°C value of the V of that voltage as the temperature changes ...

... Figure 17. The battery voltage can vary from 0 while maintaining the analog supply voltage to the TSC2102 in the range of 2 3.6 V. The input voltage (VBAT1 or VBAT2) is divided down by a factor that a 6.0-V battery voltage is represented as 1 the ADC.It is advisable to add a series resistor of 200 to 300 Ω ...

... If making measurements of BAT1, BAT2, and AUX is desired on a periodic basis, the port scan mode can be used. This mode causes the TSC2102 to sample and convert both battery inputs and the auxiliary input. At the end of this cycle, the battery and auxiliary result registers contain the updated values. Thus, with one write to the TSC2102, the host can cause three different measurements to be made. Port scan can only be done in host− ...

... Bit D8 of control register 05H/Page2 controls the VGND amplifier. A special circuit has been included in the TSC2102 to insert a short keyclick sound into the stereo audio output, even when the audio DAC is powered down. The keyclick sound is used to provide feedback to the user when a particular button is pressed or item is selected ...

... Right Channel n−1 n−2 LSB 1/fs Right Channel n−1 n−2 LSB 1/fs Right Channel n−1 n−2 2 LSB MSB TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 n− n−1 n−2 LSB MSB 23 ...

... MHz. PLL The TSC2102 has an on chip PLL to generate the needed internal audio clocks from the clock available in the system. The PLL supports a MCLK varying from 2 MHz to 50 MHz and is register programmable to enable generation of the required sampling rates from a wide range of system clocks. ...

... MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum. SLAS379A− APRIL 2003 − REVISED JUNE 2004 32768 * 2 D4 incorporates a third order multibit TSC2102 delta-sigma modulator with 25 ...

... Headphone Driver The TSC2102 features a stereo headphone driver that can deliver 25 mW per channel at 3.3-V supply, into 16-Ω load. The headphones can be connected in a single-ended configuration using ac-coupling capacitors, or the capacitors can be removed and virtual ground (VGND) connection powered ...

... The idle state of the serial clock for the TSC2102 is low, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The TSC2102 interface is designed so that with a clock phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI pin and the slave begins driving its SPIDOUT pin on the first serial clock edge. The SS pin can remain low between transmissions ...

... To read all the first page of memory, for example, the host processor must send the TSC2102 the command 0x8000 – this specifies a read operation beginning at page 0, address 0. The processor can then start clocking data out of the TSC2102. The TSC2102 automatically increments its address pointer to the end of the page; if the host processor continues clocking data out past the end of a page, the TSC2102 sends back the value 0xFFFF ...

... SS SCLK MOSI COMMAND WORD MISO Figure 25. Read Operation for TSC2102 SPI Interface SLAS379A− APRIL 2003 − REVISED JUNE 2004 DATA DATA TSC2102 29 ...

... The TSC2102 has several 16-bit registers, which allow control of the device as well as providing a location for results from the TSC2102 to be stored until read by the host microprocessor. These registers are separated into three pages of memory in the TSC2102: a data page (Page 0) and control pages (Page 1 and Page 2). The memory map is shown in Table 3. Page 0: Touch Screen Data Registers ...

... TSC2102 Data Registers (Page 0) The data registers of the TSC2102 hold data results from conversion performed by the touch screen ADC. All of these registers default to 0000H upon reset. These registers are read only Z1, Z2, BAT1, BAT2, AUX, TEMP1 and TEMP2 Registers The results of all A/D conversions are placed in the appropriate data register ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 READ/ WRITE BIT NAME RESET VALUE D13−10 ADSCM R/W 0000 D9−D8 RESOL R/W 00 D7−D6 ADAVG R/W 00 D5−D4 ADCR R FUNCTION A/D Scan Mode. 0000 => No scan 0001 => Touch screen scan function: X and Y coordinates are converted and the results returned to X and Y data registers ...

... Acts as data available (active low) only. The PINTDAV goes low as soon as one set of ADC 10 => Acts as both PEN interrupt and data available. When PEN touch is detected, PINTDAV goes 11 => Same as 10 Note: See the section Conversion Time Calculation for the TSC2102 in this data sheet for timing D13 PWRDN ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 READ/ RESET BIT NAME WRITE VALUE D7 Z2STAT Data Register Status 0 => No new data is available in Z2−data register 1 => New data is available in Z2−data register Note: This bit gets cleared only after the converted data of Z2 coordinate has been completely read ...

... Sense Time. These bits set the amount of time the TSC2102 waits to sense whether the screen is being touched, when converting a coordinate value. 32 µs 000 => 96 µs 001 => ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 PAGE 2 CONTROL REGISTER MAP REGISTER 00H: Audio Control 1 READ/ RESET BIT NAME WRITE VALUE D15−D12 R 0000 D11−D10 WLEN R/W 00 D9−D8 DATFM R/W 00 D7− D5−D0 DACFS R/W 000 REGISTER 01H: Reserved ...

... Note: This flag indicates when the soft-stepping for DAC right channel is completed DAC Channel PGA Soft-Stepping Control 0 => 0.5dB change every LRCK 1 => 0.5dB change every 2 LRCK Reserved. Write only 0 to this location. TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 FUNCTION 37 ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 REGISTER 05H: Stereo DAC Power Control READ/ RESET BIT NAME WRITE VALUE D15 PWDNC R/W 1 D14−D13 R 01 D12 DAODRC R/W 0 D11 R 1 D10 DAPWDN R VGPWDN R DAPWDF R 1 D5−D2 R 1000 ...

... Master Transfer Mode 0 => Continuous data transfer mode 1 => 256−s data transfer mode Audio Master Slave Selection 0 => TSC2102 is slave DAC 1 => TSC2102 is master DAC Reserved. Write only 000 to this location. DAC Left Channel Overflow Flag ( Read Only ) 0 => DAC left channel data is within saturation limits 1 => ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 REGISTER 0DH: Audio Bass Boost Coefficients READ/ RESET VALUE BIT NAME WRITE (IN DECIMAL) D15−D0 L_D1 R/W 32131 REGISTER 0EH: Audio Bass Boost Coefficients READ/ RESET VALUE BIT NAME WRITE (IN DECIMAL) D15−D0 ...

... Reserved. Write only 00 to this location. D value. Used when PLL is enabled. D value is valid from 0000 to 9999 in decimal. Programmed value greater than 9999 is treated as 9999 00000000000000 => 0 decimal 00000000000001 => 1 decimal 00 Reserved (write only 00) TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 FUNCTION FUNCTION FUNCTION FUNCTION 41 ...

... With this in mind, power to the TSC2102 must be clean and well bypassed. A 0.1-µF ceramic bypass capacitor must be placed as close to the device as possible. A 1-µF to 10-µF capacitor may also be needed if the impedance between the TSC2102 supply pins and the system power supply is high. The VREF pin requires a minimum bypass capacitor of 0.1 µ ...

... CONVERSION TIME CALCULATIONS FOR THE TSC2102 Touch Screen Conversion Initiated At Touch Detect The time needed to get a converted X/Y coordinate for reading can be calculated by (not including the time needed to send the command over the SPI bus PRE SNS + 2 t coordinate ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 The time for a complete X/Y/Z1/Z2 coordinate conversion is given by(not including the time needed to send the command over the SPI bus PRE SNS + 3 t coordinate 125 OSC OSC = ƒ ...

... Reading SS DEACTIVATED Z1−Data Register Sample,Conversion & Detecting Averaging for Touch Z1−Coordinate & Z2−Coordinate TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 Waiting for Host to Write Into REG−00 of PAGE−01 Touch Is Still There ) Reading Z2−Data Register Waiting for Host to Write Into REG− ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 REG−00 of Programmed PAGE−01 for Host Is Updated Controlled for Mode X−Y Scan Mode Waiting for Host to Sample,Conversion & Detecting Touch Write into REG−00 of PAGE−01 Touch Is Detected PINTDAV (As PENIRQ [D15−D14 = 00]) ...

... OSC ƒ conv SS DEACTIVATED Sample,Conversion & Averaging for of Internal Ref Mode if Applicable BAT1 & BAT2 & AUX input TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 Reading Reading AUX−Data AUX−Data Register Register Sample,Conversion & Sample,Conversion & ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 DAC CHANNEL DIGITAL FILTER DAC Channel Digital Filter Frequency Response DAC Channel Digital Filter Pass-Band Frequency Response 48 www.ti.com ...

... DEFAULT BASS-BOOST FREQUENCY RESPONSE AT 48 ksps DE-EMPHASIS FILTER FREQUENCY RESPONSE De-Emphasis Filter Response at 32 ksps TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 49 ...

... TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 De-Emphasis Error at 32 ksps De-Emphasis Filter Frequency Response at 44.1 ksps 50 www.ti.com ...

... De-Emphasis Error at 44.1 ksps De-Emphasis Frequency Response at 48 ksps TSC2102 SLAS379A− APRIL 2003 − REVISED JUNE 2004 51 ...

... De-Emphasis Error at 48 ksps PLL PROGRAMMING The on-chip PLL in the TSC2102 can be used to generate sampling clocks from a wide range of MCLK’s available in a system. The PLL works by generating oversampled clocks with respect to Fsref (44.1 kHz or 48 kHz). Frequency division generates all other internal clocks. The table below gives a sample programming for PLL registers for some standard MCLKs when PLL is required. Whenever the MCLK is of the form of N*128*Fsref (N=2,3… ...

... TSC2102IDA ACTIVE TSC2102IDAG4 ACTIVE TSC2102IDAR ACTIVE TSC2102IDARG4 ACTIVE (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design ...

... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TSC2102IDAR TSSOP DA PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 (mm) Diameter Width (mm) W1 (mm) 32 2000 330.0 24.4 8.6 Pack Materials-Page 1 19-Mar-2008 B0 (mm) K0 (mm Pin1 (mm) (mm) Quadrant 11.5 1.6 12.0 24.0 Q1 ...

... Device Package Type TSC2102IDAR TSSOP PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm 2000 Pack Materials-Page 2 19-Mar-2008 Width (mm) Height (mm) 346.0 346.0 41.0 ...

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