The TSC2301 is a highly integrated PDA analog interface circuit

TSC2301

Manufacturer Part NumberTSC2301
DescriptionThe TSC2301 is a highly integrated PDA analog interface circuit
ManufacturerTexas Instruments
TSC2301 datasheet
 


Specifications of TSC2301

Touch Panel4-WireSar Adc Resolution(bits)12
Sar Sample Rate(max)(ksps)125Vref (int/ext)Int
# Audio Dacs / Adcs2 / 2Audio Codec Resolution(bits)20
Snr Audio Dac / Adc(typ)(db)96 / 88# Audio Inputs / Outputs3 / 5
Audio Sample Rate(ksps)48Digital Audio InterfaceI2S, R, L
Control InterfaceSPIAudio Pd(mw)27
Analog Supply(v)2.7 - 3.6Additional FeaturesInt. PLL
Operating Temperature Range(c)-40 to 85Pin/package120BGA MICROSTAR JUNIOR, 64TQFP
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PROGRAMMABLE TOUCH SCREEN CONTROLLER
FEATURES
SPI™ Serial Interface
Touch Screen Controller
– 4-Wire Touch Screen Interface
– Internal Detection of Screen Touch and
Keypad Press
– Touch Pressure Measurement
– Ratiometric Conversion
– Programmable 8-, 10- or 12-Bit Resolution
– Programmable Sampling Rates Up to 125
kHz
– Direct Battery Measurement (0 to 6 V)
– On-Chip Temperature Measurement
– 4-by-4 Keypad Interface With
Programmable De-Bounce and Key
Masking
– Integrated Touch Screen Processor
Reduces Host CPU Interrupts and Overhead
– Internal Timing Control With Programmable
Delays and Averaging
Stereo Audio Codec
– 20-Bit Delta-Sigma ADC/DAC
– Dynamic Range: 98 dB
– Sampling Rate Up to 48 kHz
2
– I
S Serial Interface
– Stereo 16-
Headphone Driver
Full Power-Down Control
8-Bit Current Output DAC
On-Chip Crystal Oscillator
Programmable Bass/ Midrange/ Treble EQ
Effects Processing
6 GPIO Pins
Single 2.7-V to 3.6-V Supply
64-Pin TQFP Package
120-Ball MicroStar Junior™ BGA Package
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar Junior is a trademark of Texas Instruments.
SPI is a trademark of Motorola.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
WITH STEREO AUDIO CODEC
APPLICATIONS
Personal Digital Assistants
Cellular Phones
MP3 Players
Internet Appliances
Smartphones
DESCRIPTION
The TSC2301 is a highly integrated PDA analog
interface circuit. It contains a complete 12-bit A/D
resistive touch screen converter (ADC) including
drivers, touch pressure measurement capability,
keypad controller, and 8-bit D/A converter (DAC)
output for LCD contrast control. The TSC2301 offers
programmable resolution of 8, 10, and 12 bits and
sampling rates up to 125 kHz to accommodate
different screen sizes. The TSC2301 interfaces to the
host controller through a standard SPI serial
interface.
The TSC2301 features a high-performance 20-bit,
48-ksps stereo audio codec with highly integrated
analog functionality. The audio portion of the
TSC2301 contains microphone input with built-in
pre-amp and microphone bias circuit, an auxiliary
stereo analog input, a stereo line-level output, a
differential mono line-level output, and a stereo
headphone amplifier output. The digital audio data is
transferred through a standard I
programmable PLL for generating audio clocks from a
wide variety of system clocks is also included.
The TSC2301 also offers two battery measurement
inputs capable of battery voltages up to 6 V, while
operating at a supply voltage of only 2.7 V. It also has
an on-chip temperature sensor capable of reading
0.3°C resolution. The TSC2301 is available in 64-lead
TQFP, and 120-ball VFBGA packages.
US Patent No. 6246394
FUNCTIONAL BLOCK DIAGRAM
TSC2301
SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004
2
S interface. A fully
Copyright © 2002–2004, Texas Instruments Incorporated

TSC2301 Summary of contents

  • Page 1

    ... The TSC2301 also offers two battery measurement inputs capable of battery voltages while operating at a supply voltage of only 2 also has an on-chip temperature sensor capable of reading 0.3°C resolution. The TSC2301 is available in 64-lead TQFP, and 120-ball VFBGA packages. US Patent No. 6246394 FUNCTIONAL BLOCK DIAGRAM TSC2301 SLAS371D – ...

  • Page 2

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 AVDD - 1V AVDD 30k VCM 20k AGND Mute, 0db, 6dB, 12dB MICIN RLINEIN +12dB 35dB 0.5dB steps LLINEIN MONO+ MONO- VREF+ VREF- HPVDD Headphone HPGND Driver HPR VOUTR S VOUTL HPL Headphone Driver ...

  • Page 3

    ... SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 ORDERING TRANSPORT MEDIA NUMBER QUANTITY TSC2301IPAG Trays, 160 TSC2301IPAGR Tape and reel, 1500 TSC2301IGQZ Trays, 250 TSC2301IGQZR Tape and reel, 2500 TSC2301IZQZ Trays, 250 TSC2301IZQZR Tape and reel, 2500 TSC2301 4 V ±0 ( ( -40° ...

  • Page 4

    ... Line, Mic inputs Line outputs ADC performance measured using kHz No input 1 kHz, -0.5 dB input DAC performance measured at Line Outputs using kHz No input 1-kHz, 0-dB input DAC playback through headphone driver www.ti.com TSC2301 Units Min Typ Max 0 +VREFIN 25 1 µA 0 6.0 25 ± ...

  • Page 5

    ... TTL loads TTL loads OL 1-kHz SAR sample rate, external V ref 20-kHz SAR sample rate, internal V ref 44.1-kHz Playback 2.7V DD Mono 8-kHz record 2.7V DD Audio fully powered down TSC2301 TSC2301 Units Min Typ Max -83 - ...

  • Page 6

    ... I I I/O GPIO_5/CLKO PIN ASSIGNMENT (TOP VIEW TSC2301 PIN DESCRIPTION NAME DESCRIPTION VBAT1 Battery monitor input 1 VBAT2 Battery monitor input 2 VREFIN SAR reference voltage ...

  • Page 7

    ... AVDD Analog supply HPL Headphone amplifier left output HPR Headphone amplifier right output HPGND Analog ground for headphone amplifier and touch screen circuitry X- X- position input Y- Y- position input X+ X+ position input TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 7 ...

  • Page 8

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 VFBGA TQFP I/O BALL PIN D10 61 I C11 62 I B11 63 I B10 Lead SCLK t w sck t v MSB OUT MISO MSB IN MOSI TIMING CHARACTERISTICS All specifications typical at -40°C to +85°C, +V ...

  • Page 9

    ... Temperature (5C) Figure 2. INTERNAL 1.25-V REFERENCE vs TEMPERATURE 1.202 1.201 1.2 1.199 1.198 1.197 1.196 1.195 1.194 1.193 –50 50 100 0 Temperature (5C) Figure 5. TSC2301 CONVERSION SUPPLY CURRENT vs TEMPERATURE 2 1.95 1.9 1.85 1.8 1.75 1.7 1.65 1.6 – 100 Temperature (5C) Figure 3. INTERNAL OSCILLATOR FREQUENCY vs TEMPERATURE 9.1 9 8.9 8.8 osc 8.7 8.6 8.5 8.4 –50 ...

  • Page 10

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued +25° REF INTERNAL 2.5-V REFERENCE vs TEMPERATURE 2.5 2.495 2.49 2.485 2.48 2.475 2.47 2.465 2.46 – 100 Temperature (C) Figure 7. TEMP1 DIODE VOLTAGE vs TEMPERATURE 750 700 650 600 550 500 450 400 – ...

  • Page 11

    ... SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 SNR OF ADC (LINEIN) vs TEMPERATURE 100 80 –60 –40 – Temperature (5C) Figure 15. THD OF BYPASS PATH vs TEMPERATURE –98.0 –99.0 –100.0 –101.0 –102.0 –103.0 –60 –40 – 100 Temperature (5C) Figure 18. TSC2301 60 80 100 60 80 100 11 ...

  • Page 12

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued +25° REF SNR OF BYPASS PATH vs TEMPERATURE 102 101 100 –60 –40 – Temperature (5C) Figure 19. 1.25-V REFERENCE vs SUPPLY VOLTAGE 1.2005 1.2004 1.2003 1.2002 1 ...

  • Page 13

    ... Vdd (V) Figure 26. PD SUPPLY CURRENT vs SUPPLY VOLTAGE 0.45 0.375 0.3 0.225 0.15 0.075 0 2.5 3 3.5 Vdd (V) Figure 29. TSC2301 INTERNAL OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE 9 8.9 8.8 8.7 8.6 8.5 2.5 3 3.5 Vdd (V) Figure 27. INL MAXIMUM vs SUPPLY VOLTAGE 4.5 4.25 4 3.75 3.5 3.25 3 2.5 3 3.5 Vdd (V) Figure 30. ...

  • Page 14

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued +25° REF INL MINIMUM vs SUPPLY VOLTAGE –1.5 –1.75 –2 –2.25 –2.5 –2.75 –3 2.5 3 3.5 Vdd (V) Figure 31. THD OF DAC (LINEOUT) vs SUPPLY VOLTAGE –95 –96 –97 –98 –99 – ...

  • Page 15

    ... Vdd (V) Figure 38. SNR OF BYPASS PATH vs SUPPLY VOLTAGE 102 101 100 2.5 3 3.5 Vdd (V) Figure 41. TSC2301 SNR OF DAC (HP DRIVER) vs SUPPLY VOLTAGE 2.5 3 3.5 Vdd (V) Figure 39. THD OF MONO PATH vs SUPPLY VOLTAGE –95 –96 –97 –98 –99 – ...

  • Page 16

    ... Registers control the operation of the touch screen A/D converter, keypad scanner, and audio codec. The result of measurements made are placed in the TSC2301 memory map and can be read by the host at any time. Three signals are available from the TSC2301 to indicate that data is available for the host to read. The DAV output indicates that an analog-to-digital conversion has completed and that data is available ...

  • Page 17

    ... R1 RESET KBIRQ 29 D DGND DVDD 28 0 I2SDOUT D 26 I2SDIN 25 LRCLK 24 BCLK 23 MCLK 22 COO 21 COI 20 DAV 19 SPI_DOUT 18 SPI_DIN 17 SPI_CLK 0 TSC2301 ...

  • Page 18

    ... X+ input to the ADC input, driving Y+ to +VDD and Y- to GND using switches internal to the TSC2301, and digitizing the voltage seen at the X+ input. The voltage measured is determined by the voltage divider developed at the point of touch. For this measurement, the horizontal panel resistance in the X+ lead does not affect the conversion, due to the high input impedance of the ADC ...

  • Page 19

    ... This is referred to as the panel voltage stabilization time, and is used in some of the modes available in the TSC2301. In other modes, the TSC2301 can be commanded to turn on the drivers only without performing a conversion. Time can then be allowed before the command is issued to perform a conversion ...

  • Page 20

    ... Figure 47. Simplified Diagram of the Touch Screen Analog Input Section Data Format The TSC2301 output data is in straight binary format as shown in code for the given input voltage and does not include the effects of offset, gain, or noise. Figure 48. Ideal Input Voltages and Output Codes ...

  • Page 21

    ... Reference The TSC2301 has an internal voltage reference that can be set to 1 2.5 V, through the reference control register. This reference can also be set to automatically power down between conversions to save power, or remain on to reduce settling time. The internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs ...

  • Page 22

    ... Y– Figure 49. PENIRQ Functional Block Diagram In modes where the TSC2301 needs to detect if the screen is still touched (for example, when doing a PENIRQ-initiated X, Y, and Z conversion), the TSC2301 must reconnect the drivers so that the 50-k connected again. Because of the high value of this pullup resistor, any capacitance on the touch screen inputs cause a long delay time, and may prevent the detection from occurring correctly ...

  • Page 23

    ... MISO pin to the master shift register. When the POL pin of the TSC2301 is tied high (POL=1), the idle state of the serial clock for the TSC2301 is low, which corresponds to a clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). When the POL pin of the TSC2301 is tied low (POL=0), the idle state of the serial clock is high, which corresponds to a clock polarity setting of 1 (typical microprocessor SPI control bit CPOL = 1) ...

  • Page 24

    ... PG1 set to 1, and the ADDR bits set to 07h. This results in the address pointer pointing at the location of the first bass-boost coefficient in memory see (Page 2). See the section on the TSC2301 memory map for details of register locations Bit SBBit Bit Bit Bit ...

  • Page 25

    ... The TSC2301 has several 16-bit registers that allow control of the device as well as providing a location for results from the TSC2301 to be stored until read by the host microprocessor. These registers are separated into three pages of memory in the TSC2301: a data page (Page 0), a control page (Page 1), and an audio control page (Page 2). The memory map is shown in ...

  • Page 26

    ... Table 4. Register Summary for TSC2301 D13 D12 D11 D10 R11 R10 R11 R10 R11 R10 ...

  • Page 27

    ... Table 4. Register Summary for TSC2301 (continued) PAGE ADDR REGISTER D15 D14 D13 (HEX) NAME 1 0F reserved KPMASK M15 M14 M13 1 11 reserved reserved reserved reserved reserved reserved ...

  • Page 28

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 4. Register Summary for TSC2301 (continued) PAGE ADDR REGISTER D15 D14 (HEX) NAME 2 1B ADCLKCF reserved reserved reserved reserved D13 D12 D11 D10 ...

  • Page 29

    ... Pen Status/Control Mode. Reading this bit allows the host to determine if the screen is touched. Writing to this bit determines the mode used to read coordinates: host controlled or under control of the TSC2301 responding to a screen touch. When reading, the PENSTS bit indicates if the pen is down or not. When writing to this register, this bit determines if the TSC2301 controls the reading of coordinates the coordinate conversions are host-controlled ...

  • Page 30

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [13:10] — AD3 - AD0 ADC Function Select bits. These bits control which input converted, and what mode the converter is placed in. These bits are the same whether reading or writing. See bits are used. ...

  • Page 31

    ... Table 11 for settings of these bits. The default state is 000, indicating a 0µs PV0 0 0 µs (default) 1 100 µs 0 500 µ 100 ms TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Stabilization Time 31 ...

  • Page 32

    ... X Bit 4 —INT Internal Reference Mode. If this bit is written the TSC2301 uses its internal reference; if this bit the part assumes an external reference is being supplied. The default state for this bit is to select an external reference (0). This bit is the same whether reading or writing. ...

  • Page 33

    ... Reference Voltage Control. This bit selects the internal reference voltage, either 1 2.5 V. The default value is 1.2 V. This bit is the same whether reading or writing. Value 0 1 TSC2301 Configuration Control Register (Page 1, Address 05H) This control register controls the configuration of the precharge and sense times for the touch detect circuit. The register is formatted as follows: Bit 15 Bit 14 ...

  • Page 34

    ... PRE2 Bits [2:0] — SNS[2:0] Sense time selection bits. These bits set the amount of time the TSC2301 waits to sense a screen touch between coordinate axis conversions in self-controlled mode. SNS2 Table 18 ...

  • Page 35

    ... TSC2301 KEYPAD REGISTERS The keypad scanner hardware in the TSC2301 is controlled by two registers: the keypad control register and the keypad mask register. The keypad control register controls general keypad functions such as scanning and de-bouncing, while the keypad mask register allows you to mask certain keys from being detected at all. ...

  • Page 36

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Keypad Mask Register (Page 1, Address 10H) The Keypad Mask register is formatted as follows: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 MSB M15 M14 M13 M12 M11 This is the same format as used in the keypad data register (Page 0, Address 04H). Each bit in these registers represents one key on the keypad ...

  • Page 37

    ... SPI interface to see whether data is available, without dedicating a GPIO pin from the host processor to the TSC2301 DAV pin. This bit is normally high, goes low when touch screen or keypad data is available, and is reset high when all the new data has been read. When written to, this bit becomes KBC1, operation detailed below ...

  • Page 38

    ... When using a nonaudio standard MCLK frequency or crystal that is not covered by any of the automatic PLL settings in MCLK[1:0], the user must manually configure the TSC2301 PLL to generate the proper clock for the audio data converters. The proper clock for any sampling rates that are submultiples of 44.1 kHz is 512 x 44.1 kHz = 22 ...

  • Page 39

    ... OPERATION - TOUCH SCREEN MEASUREMENTS Conversion Controlled by TSC2301 Initiated at Touch Detect In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low. At the same time, the TSC2301 powers up its internal clock. It then turns on the Y-drivers, and after a programmed panel voltage stabilization time, powers up the ADC and convert the Y coordinate. If averaging is selected, several conversions may take place ...

  • Page 40

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 If only X and Y coordinates are to be measured, then the conversion process is complete. flowchart for this process. The time it takes to go through this process depends upon the selected resolution, internal conversion clock rate, averaging selected, panel voltage stabilization time, and precharge and sense times ...

  • Page 41

    ... Figure 51. X & Y Coordinate Touch Screen Scan, Initiated by Touch SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Go To Host Controlled Conversion Turn off clock Reset PENIRQ and Scan N Trigger Done TSC2301 Turn On Drivers: X Panel Voltage Stabilization Done Y Power up ADC Convert X coordinates Is Data ...

  • Page 42

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Touch Screen Scan X, Y and Z PENIRQ Initiated Screen Touch Issue Interrupt PENIRQ Host Controlled Is PENSTS =1 Conversion Y Start Clock Turn On Drivers: Y Panel Voltage Stabilization Done Y Power up ADC Convert Y coordinates N Is Data ...

  • Page 43

    ... In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low. The host recognizes the interrupt request, and then writes to the ADC control register to select one of the touch screen scan functions (single X-, Y-, or Z-conversions, continuous X/Y or X/Y/Z1/Z2 Conversions) ...

  • Page 44

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Screen Touch Issue Interrupt PENIRQ Is PENSTS =1 Host Writes A/D Converter Control Register Reset PENIRQ Start Clock Turn On Drivers: Y Panel Voltage Stabilization Done Y Power up ADC Convert Y coordinates N Is Data Averaging Done Y Store Y Coordinates in Y ...

  • Page 45

    ... Convert X coordinates Is Data N Averaging Done Y Store X Coordinates in X Register Power Down ADC Turn off clock Is Screen Touched Reset PENIRQ and Scan Trigger Done TSC2301 Turn On Drivers: Y Panel Voltage Stabilization Done Y Power up ADC Convert Z1 coordinates Is Data N Averaging Done Y Store Z1 Coordinates ...

  • Page 46

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Touch Screen Scan X Coordinate Host Initiated Screen Touch Issue Interrupt PENIRQ Is PENSTS =1 Host Writes A/D Converter Control Register Reset PENIRQ Are Drivers On Y Start Clock Power up ADC Figure 55. X Coordinate Reading Initiated by Host ...

  • Page 47

    ... Figure 56. Y Coordinate Reading Initiated by Host SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Go To Host Controlled Conversion Done Start Clock Turn On Drivers: Y Panel Voltage Stabilization Done TSC2301 Store Y Coordinates in Y Register Power Down ADC Set /DAV = 0 Turn off clock Done 47 ...

  • Page 48

    ... N Averaging Done Y Store Z1 Coordinates in Z1 Register Figure 57. Z Coordinate Reading Initiated by Host Conversion Controlled by the Host In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low. The Host N Controlled Conversion DONE N Start Clock ...

  • Page 49

    ... An example sequence would be: (a) PENIRQ goes low when screen is touched. (b) Host writes to TSC2301 to turn on X-drivers. (c) Host waits a desired delay for panel voltage stabilization. (d) Host writes to TSC2301 to begin X-conversion. After waiting for the settling time, the host then addresses the TSC2301 again, this time requesting an X coordinate conversion ...

  • Page 50

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Screen Touch Issue Interrupt PENIRQ Go To Host Controlled N Is PENSTS =1 Host Writes A/D Converter Control Register Reset PENIRQ Turn On Drivers: X Done Figure 58. X Coordinate Reading Controlled by Host 50 Host Controlled X Coordinate Start Clock ...

  • Page 51

    ... Done Figure 59. Y Coordinate Reading Controlled by Host SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Host Controlled Y Coordinate Start Clock Turn On Drivers: Y Done Is Panel Voltage Stabilization Done N TSC2301 Host Writes A/D Converter Control Register Are Drivers Start Clock Y Power up ADC ...

  • Page 52

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Screen Touch Issue Interrupt PENIRQ Is PENSTS =1 Host Writes A/D Converter Control Register Reset PENIRQ Turn On Drivers: X Done Host Writes A/D Converter Control Register Reset PENIRQ Are Drivers On Y Start Clock Power up ADC Convert Z1 ...

  • Page 53

    ... During the final test of the end product, the diode voltage would be measured by the TSC2301 ADC at a known room temperature, and the corresponding digital code stored in system memory, for calibration purposes by the user. The result is an equivalent temperature measurement resolution of 0.3° ...

  • Page 54

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 N Figure 62. Single Temperature Measurement Mode 54 Temperature Input 1 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Programmed Delay) Power up ADC Convert Temperature Input 1 Is Data Averaging Done Y Store Temperature Input 1 in TEMP1 Register www ...

  • Page 55

    ... TSC2301. An example of this is shown may be regulated by a dc/dc converter or low-dropout regulator to provide a lower supply voltage to the TSC2301. The battery voltage can vary from 0 while maintaining the voltage to the TSC2301 at a level of 2.7 V-3.6 V. The input voltage the A/D, while the input voltage ...

  • Page 56

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Figure 64. VBAT Example Battery Measurement Functional Block Diagrams, VDD = 2 Flowcharts which detail the process of making a battery input reading are shown in The time needed to make temperature, auxiliary, or battery measurements is given by 2.625 ...

  • Page 57

    ... Power up ADC Convert Battery Input 1 Is Data Averagin Done Y Store Battery Input 1 in BAT1 Register Figure 65. V Measurement Process BAT1 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Power Down ADC Power Down Reference Set /DAV = 0 Turn off clock DONE TSC2301 57 ...

  • Page 58

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 N OPERATION - AUXILIARY MEASUREMENT The two auxiliary voltage inputs can be measured in similar fashion to the battery inputs, with no voltage dividers. The input range of the auxiliary inputs for this feature may include external temperature sensing, ambient light monitoring for controlling an LCD back-light, or sensing the current drawn from the battery ...

  • Page 59

    ... Figure 67. AUX1 Measurement Process Auxiliary Input 1 Host Writes A/D Register Start Clock (Including Delay) Power Down ADC Power up ADC Power Down Reference Convert Auxiliary Input 1 Set /DAV = 0 Is Data Averaging Turn off clock Done Y TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 DONE 59 ...

  • Page 60

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 60 Auxiliary Input 2 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Delay) Power up ADC Convert Auxiliary Input 2 Is Data N Averaging Done Y Store Auxiliary Input 2 in AUX2 Register Figure 68. AUX2 Measurement Process www ...

  • Page 61

    ... If measurements of all the battery and auxiliary inputs are required, the port scan mode can be used. This mode causes the TSC2301 to sample and convert both battery inputs and both auxiliary inputs. At the end of this cycle, the battery and auxiliary data registers contain the updated values, and the DAV pin is asserted low, signaling the host to read the data ...

  • Page 62

    ... LCD contrast control bias. V+ can be a higher voltage than the supply voltage for the TSC2301. The only restriction is that the voltage on the AOUT pin can never go above the absolute maximum ratings for the device, and should stay above 1.5 V for linear operation. ...

  • Page 63

    ... Figure 71. DAC Output Current Range vs RRNG Resistor Value For example, consider an LCD that has a contrast control voltage VBIAS that can range from that draws 400 µA when used, and has an available 5-V supply. This is higher than the TSC2301 supply voltage, but it is within the absolute maximum ratings. ...

  • Page 64

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Figure 72. DAC Circuit When Using V+ Higher Than 2N3904 AOUT VDD DAC 8–Bits ARNG RRNG www.ti.com V BIAS . supply ...

  • Page 65

    ... OPERATION - KEYPAD INTERFACE The TSC2301 contains a keypad interface that is suitable for use with matrix keypads keys. A control register, the keypad control register, is used to set the scan rate for the keypad and de-bounce times. There is also a keypad mask register which allows certain keys to be masked from being read, or from causing the TSC2301 to detect a key-press on selected keys ...

  • Page 66

    ... I2SDOUT (pin 27). For the TSC2301, these formats are selected through the I2SFM bits in Reg 00h The following figures illustrate audio data input/output formats and timing. The TSC2301 can accept 32-, 48-, or 64-bit clocks (BCKIN) in one clock of LRCIN. Only 16-bit data formats can be selected when 32-bit clocks/LRCIN are applied. ...

  • Page 67

    ... LSB MSB SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 R– MSB R– LSB R– MSB R– LSB R– LSB R– LSB TSC2301 LSB 1 LSB ...

  • Page 68

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 – – LRCIN BCKIN I2SDIN – – LRCIN BCKIN I2SDOUT ...

  • Page 69

    ... Table 29. Audio Data Input/Output Timing (continued) Parameter Falling time to all signals TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Symbol Min t FALL Max ...

  • Page 70

    ... SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Audio Data Converters The TSC2301 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are both capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz kHz. ...

  • Page 71

    ... This transfer function(s) can be determined by the user and loaded to the TSC2301 at power-up, and the feature can then be switched on or off by the user during normal operation filter with gain over designed and used, and large-scale signals are played at high amplitude through the DAC, overloading and undesirable effects can occur ...

  • Page 72

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 27618 32130 -27033 -31505 26461 which implements the bass-boost transfer function shown in above approximately 150 Hz when operating at a 48-kHz sampling rate. All coefficients are represented by 16-bit twos complement integers with values ranging from -32768 to 32767. ...

  • Page 73

    ... Differential Monophonic Output (MONO+/-) The differential mono output of the TSC2301 can be used to drive a power amplifier which drives a low-impedance speaker. This block can output either a mono mix of the stereo line outputs, or the analog input to the left-channel ADC ...

  • Page 74

    ... TSC2301 AUDIO CONTROL REGISTERS TSC2301 Audio Control Register (Page 2, Address 00H) The audio control register of the TSC2301 controls the digital audio interface, the microphone preamp gain, the record multiplexer settings, and the ADC highpass filter pole. This register determines which ADC high pass filter response is selected, as well as which audio inputs are connected to the stereo ADCs ...

  • Page 75

    ... ADCR input = MIC (default) 1 ADCR input = LLINEIN 0 ADCR input = RLINEIN 1 ADCR input = (RLINEIN+LLINEIN)/2 Table 34. Microphone Input Gain Selection MICG[1:0] MICG0 Description 0 MIC gain = 0 dB (default) 1 MIC gain = MIC gain = MIC gain = 12 dB TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 75 ...

  • Page 76

    ... The ADC volume control register controls the independent programmable gain amplifiers (PGA's) on the left and right channel inputs to the audio ADCs of the TSC2301. The gain of these PGAs can be adjusted from - 0.5-dB steps. The ADC inputs can also be hard-muted, or internally shorted to VCM so that no input signal is seen ...

  • Page 77

    ... The DAC volume control register controls the independent digital gain controls on the left and right channel audio DAC's of the TSC2301. The gain of the DACs can be adjusted from -63 0.5-dB steps. The DAC inputs can also be muted, so that all zeroes are sent to the DAC interpolation filters. ...

  • Page 78

    ... TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 The DAC volume control register is formatted as follows: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 MSB DAMU DAVL DAVL5 DAVL4 DAVL3 DAVL DAVL DAVL L 6 Bit 15 — DAMUL Left DAC Mute. This bit is used to mute the input to the left channel DAC. The user can set this bit to mute the DAC while retaining the previous gain setting in DAVL[6:0], so that the gain control returns to the previous gain setting when DAMUL is cleared ...

  • Page 79

    ... A/D or D/A conversion. This feature can be used for playback of an external analog source, such stereo tuner through the TSC2301's headphone amplifier. The gain of these PGA's can be adjusted from -35 0.5 dB steps. The bypass paths can also be muted, so that no signal is transmitted. ...

  • Page 80

    ... BPVR[6:0] = 0d-31d = mute KEYCLICK CONTROL REGISTER (Page 2, Address 04H) The Keyclick Control Register of the TSC2301 controls the setup of the internal keyclick sound generator. This register is used to initiate and set the frequency, amplitude, and duration of the internally generated keyclick sound. This register also controls the input to the differential mono output, and the soft-stepping function of the TSC2301 volume controls ...

  • Page 81

    ... KCFR0 Keyclick Tone Frequency 0 62 125 Hz 0 250 Hz 1 500 (default Table 46. Mono Select Description Mono output comes from left ADC input (default). Mono output comes from mono mix of line outputs. TSC2301 (14) 81 ...

  • Page 82

    ... The audio power / miscellaneous control register of the TSC2301 controls the powering down of various audio blocks of the TSC2301. The default state of the TSC2301 has all audio blocks powered down. Before using any of the audio blocks, they must be powered up by writing to this register. This register also controls the crystal oscillator clock and buffer, the bass-boost filter, and the de-emphasis filter ...

  • Page 83

    ... Power up/down is not complete. Power up/down is complete (default). Table 50. Microphone Bias Power Down Description Microphone bias is on. Microphone bias is off (default). Table 51. Crystal Oscillator Control Description Crystal oscillator is off (default). Crystal oscillator is on. TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 83 ...

  • Page 84

    ... GPIO CONTROL REGISTER (Page 02, Address 06h) The GPIO control register controls the GPIO pins of the TSC2301. The direction of each GPIO pin can be set independently. For GPIOs configured as output pins, the data to be driven is written to this register. For GPIO's configured as inputs, the input data can be read from this register. This register also contains a bit, SDAVB which mirrors the state of the DAVB output line ...

  • Page 85

    ... These bits are reserved and should be written read, they read back as 0. Bits [13:8] — IO5- IO0 GPIO Directional Control. These 6 bits control the direction of the TSC2301s six GPIO pins. When one of these bits is set to one, the corresponding GPIO pin is configured as an output. When one of these bits is set to zero, the corresponding GPIO pin is configured as an input. The default setting of these bits is zero (all inputs). Bits 7,6 — ...

  • Page 86

    ... Still, each situation is unique and the following suggestions should be reviewed carefully. For optimum performance, care must be taken with the physical layout of the TSC2301 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator ...

  • Page 87

    ... AVDD). With this in mind, power to the TSC2301 must be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible on each supply pin to its respective ground pin. A 1-µF to 10-µ ...

  • Page 88

    ... Status TSC2301IPAG ACTIVE TQFP TSC2301IPAGG4 ACTIVE TQFP TSC2301IPAGR ACTIVE TQFP TSC2301IPAGRG4 ACTIVE TQFP TSC2301IZQZ ACTIVE BGA MICROSTAR JUNIOR TSC2301IZQZR ACTIVE BGA MICROSTAR JUNIOR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. ...

  • Page 89

    TI and TI suppliers consider certain information to be proprietary, and thus CAS ...

  • Page 90

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing TSC2301IPAGR TQFP PAG TSC2301IZQZR BGA MI ZQZ CROSTA R JUNI OR PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 64 1500 330.0 24.4 13.0 120 2500 330.0 16.4 6.3 Pack Materials-Page 1 ...

  • Page 91

    ... Device Package Type TSC2301IPAGR TQFP TSC2301IZQZR BGA MICROSTAR JUNIOR PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) PAG 64 1500 ZQZ 120 2500 Pack Materials-Page 2 16-Feb-2012 Width (mm) Height (mm) 346.0 346.0 41.0 336.6 336.6 28.6 ...

  • Page 92

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  • Page 93

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  • Page 94

    PAG (S-PQFP-G64) 0, 7,50 TYP 10,20 SQ 9,80 12,20 SQ 11,80 1,05 0,95 1,20 MAX NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC ...

  • Page 95

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...