The ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers

ADS41B25

Manufacturer Part NumberADS41B25
DescriptionThe ADS41B25 is a member of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers
ManufacturerTexas Instruments
ADS41B25 datasheet
 


Specifications of ADS41B25

Resolution(bits)12Sample Rate (max)(sps)125MSPS
# Input Channels1Snr(db)68.8
Sfdr(db)89Power Consumption(typ)(mw)310
Operating Temperature Range(c)-40 to 85InterfaceParallel CMOS,Parallel LVDS
Analog Voltage Av/dd(min)(v)1.7Analog Voltage Av/dd(max)(v)1.9
Digital Supply(min)(v)1.7Digital Supply(max)(v)1.9
ArchitecturePipelineInl(max)(+/-lsb)3.5
Sinad(db)68.8Enob(bits)11.1
Input Range1.5V (p-p)Reference ModeInt
Analog Input Bw(mhz)800Pin/package48VQFN
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12-Bit, 125MSPS, Ultralow-Power ADC with Analog Buffer
FEATURES
1
• Resolution: 12-Bit, 125MSPS
23
Integrated High-Impedance
Analog Input Buffer:
– Input Capacitance at dc: 3.5pF
– Input Resistance at dc: 10kΩ
Maximum Sample Rate: 125MSPS
Ultralow Power:
– 1.8V Analog Power: 114mW
– 3.3V Buffer Power: 96mW
– I/O Power: 100mW (DDR LVDS)
High Dynamic Performance:
– SNR: 68.3dBFS at 170MHz
– SFDR: 87dBc at 170MHz
Output Interface:
– Double Data Rate (DDR) LVDS with
Programmable Swing and Strength:
– Standard Swing: 350mV
– Low Swing: 200mV
– Default Strength: 100Ω Termination
– 2x Strength: 50Ω Termination
– 1.8V Parallel CMOS Interface Also
Supported
Programmable Gain for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-48 (7mm × 7mm)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Incorporated.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Check for Samples:
ADS41B25
DESCRIPTION
The ADS41B25 is a member of the ultralow-power
ADS4xxx analog-to-digital converter (ADC) family,
featuring integrated analog input buffers. This device
uses innovative design techniques to achieve high
dynamic performance, while consuming extremely
low power. The analog input pins have buffers, with
the benefits of constant performance and input
impedance across a wide frequency range. The
device is well-suited for multi-carrier, wide bandwidth
communications
linearization.
The ADS41B25 has features such as digital gain and
offset correction. The gain option can be used to
improve SFDR performance at lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be used to
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operates at
scaled-down power with no loss in performance.
The device supports both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rate of
the DDR LVDS interface (maximum 500MBPS)
makes it possible to use low-cost field-programmable
gate array (FPGA)-based receivers. The device has a
low-swing LVDS mode that can be used to further
reduce the power consumption. The strength of the
LVDS output buffers can also be increased to support
50Ω differential termination.
The device is available in a compact QFN-48
package
and
is
temperature range (–40°C to +85°C).
ADS41B25
SBAS548 – JUNE 2011
applications
such
as
PA
specified
over
the
industrial
Copyright © 2011, Texas Instruments Incorporated

ADS41B25 Summary of contents

  • Page 1

    ... The device is well-suited for multi-carrier, wide bandwidth communications linearization. The ADS41B25 has features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset ...

  • Page 2

    ... Quality and Lead-Free (Pb-Free) Data (1) (2) , RESET, SCLK, (1) Product Folder Link(s): ADS41B25 www.ti.com PACKAGE ORDERING TRANSPORT MARKING NUMBER MEDIA ADS41B25IRGZR Tape and reel AZ41B25 ADS41B25IRGZT Tape and reel web site for more ADS41B25 MIN MAX UNIT –0.3 2.1 V –0.3 3.9 V –0.3 2.1 V –0.3 0.3 V –2.4 2.4 V –2.4 2 ...

  • Page 3

    ... Note that these modes cannot be set when the serial interface is not used (when the RESET pin is tied high); see the Configuration section. Copyright © 2011, Texas Instruments Incorporated (2) (2) section in Application Information Application Information. (1) (2) (3) HIGH-PERFORMANCE MODES DESCRIPTION Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 ADS41B25 MIN TYP MAX UNIT 1.7 1.8 1 3.3 3.6 V 1.7 1.8 1 ...

  • Page 4

    ... ADS41B25 SBAS548 – JUNE 2011 ELECTRICAL CHARACTERISTICS: ADS41B25 Typical values are at +25°C, AVDD = 1.8V, AVDD_BUF = 3.3V, DRVDD = 1.8V, 1.5V cycle, –1dBFS differential analog input, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range –40° MIN ...

  • Page 5

    ... Copyright © 2011, Texas Instruments Incorporated = –40° MIN ADS41B25 MIN VCM –15 E –2 GREF E GCHAN section in the Application Information). Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 = +85°C, AVDD = 1.8V, MAX TYP MAX UNIT 1 kΩ 3.5 pF 800 MHz µA ...

  • Page 6

    ... LOW DRVDD – 0.1 V Standard swing LVDS 270 ODH –430 V Standard swing LVDS ODL V Low swing LVDS ODH V Low swing LVDS ODL V 0.85 OCM Product Folder Link(s): ADS41B25 www.ti.com ADS41B25 TYP MAX UNIT 1.3 V 0.4 V 1.3 V 0.4 V µ µA 0 µA –10 µA DRVDD ...

  • Page 7

    ... This pin functions as a serial interface data input when RESET is low. When 1 I RESET is high, SDATA functions as a STANDBY control pin (see This pin has an internal 180kΩ pull-down resistor. Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 37 36 DRGND 35 DRVDD ...

  • Page 8

    ... SERIAL READOUT = 1. This pin is a CMOS output level pin (powered from DRVDD 1.8V digital and output buffer supply 2 I Digital and output buffer ground 1 — Not used 4 — Do not connect Product Folder Link(s): ADS41B25 www.ti.com DESCRIPTION Table 3 for detailed Copyright © 2011, Texas Instruments Incorporated ...

  • Page 9

    ... This pin functions as a serial interface data input when RESET is low. When 1 I RESET is high, SDATA functions as a STANDBY control pin (see pin has an internal 180kΩ pull-down resistor. Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 37 36 DRGND 35 DRVDD ...

  • Page 10

    ... READOUT = 0, and functions as a serial register readout pin when READOUT = 1. This pin is a 1.8V CMOS output pin (powered from DRVDD 1.8V digital and output buffer supply 2 I Digital and output buffer ground 4 — Do not connect Product Folder Link(s): ADS41B25 www.ti.com DESCRIPTION Table 3). Copyright © 2011, Texas Instruments Incorporated ...

  • Page 11

    ... Common 12-Bit Digital Functions ADC Control Reference Interface Figure 3. Block Diagram Logic 0 V ODL Figure 4. LVDS Output Voltage Levels Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 DDR LVDS Interface CLKOUTP CLKOUTM D0_D1_P D0_D1_M D2_D3_P D2_D3_M D4_D5_P D4_D5_M DDR Serializer ...

  • Page 12

    ... Duty cycle of output clock, CLKOUT 1MSPS ≤ sampling frequency ≤ 125MSPS 1MSPS ≤ sampling frequency ≤ 125MSPS 1MSPS ≤ sampling frequency ≤ 125MSPS Time to valid data after OE becomes active Product Folder Link(s): ADS41B25 www.ti.com MIN TYP MAX UNIT 0.6 ...

  • Page 13

    ... (1) 21 Clock Cycles Figure 5. Latency Diagram Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 HOLD TIME (ns) TYP MAX 0.6 0.6 t (ns) PDI MAX MIN TYP MAX PDI ...

  • Page 14

    ... Dn_Dn + 1_P ( Dn_Dn + 1_M Figure 6. LVDS Mode Timing PDI CLKOUT ( START Figure 7. CMOS Mode Timing Product Folder Link(s): ADS41B25 www.ti.com t H (1) Copyright © 2011, Texas Instruments Incorporated ...

  • Page 15

    ... The ADS41B25 has several modes that can be configured using a serial programming interface, as described in Table 3, Table 4, and Table 5. In addition, the device has two dedicated parallel pins to quickly configure commonly-used functions. The parallel pins are DFS (analog four-level control pin) and OE (digital control pin). ...

  • Page 16

    ... SDATA hold time DH 16 Submit Documentation Feedback SCLK Figure 9. Serial Interface Timing MIN ) > dc SCLK Product Folder Link(s): ADS41B25 www.ti.com Register Data DSU t SLOADH = –40° +85°C, MIN MAX TYP MAX UNIT ...

  • Page 17

    ... Copyright © 2011, Texas Instruments Incorporated Enable Serial Readout (READOUT = 1) Register Data D[7: (don’t care Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 Register Data D[7:0] = 01h ...

  • Page 18

    ... Submit Documentation Feedback Figure 11. Reset Timing Diagram TEST CONDITIONS MIN pulse active serial registers 100 Product Folder Link(s): ADS41B25 www.ti.com –40° +85°C, MIN MAX TYP MAX UNIT ...

  • Page 19

    ... GLOBAL OFFSET PEDESTAL 0 OFFSET CORR TIME CONSTANT 0 0 LOW SPEED Register Address 00h (Default = 00h Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 ( RESET READOUT HIGH PERF MODE 1 0 TEST PATTERNS ...

  • Page 20

    ... For best performance across sampling clock and input signal frequencies, set the HIGH PERF MODE 1 bits 20 Submit Documentation Feedback Register Address 01h (Default = 00h LVDS SWING (1) Register Address 03h (Default = 00h Product Folder Link(s): ADS41B25 www.ti.com PERF MODE 1 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 21

    ... Output custom pattern (use registers 3Fh and 40h for setting the custom pattern) 110 = Unused 111 = Unused Copyright © 2011, Texas Instruments Incorporated Register Address 25h (Default = 50h Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 TEST PATTERNS Submit Documentation Feedback 21 ...

  • Page 22

    ... Register Address 3Fh (Default = 00h CUSTOM CUSTOM PATTERN D10 PATTERN D9 Register Address 40h (Default = 00h CUSTOM CUSTOM PATTERN D2 PATTERN D1 Product Folder Link(s): ADS41B25 www.ti.com LVDS CLKOUT LVDS DATA 0 STRENGTH STRENGTH CUSTOM ...

  • Page 23

    ... Disables control of output clock fall edge 1 = Enables control of output clock fall edge Copyright © 2011, Texas Instruments Incorporated Register Address 41h (Default = 00h CLKOUT RISE Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 CLKOUT CLKOUT RISE POSN FALL Submit Documentation Feedback 23 ...

  • Page 24

    ... Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast Bits[1:0] Always write '0' 24 Submit Documentation Feedback Register Address 42h (Default = 08h Product Folder Link(s): ADS41B25 www.ti.com STBY 0 0 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 25

    ... For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit Copyright © 2011, Texas Instruments Incorporated Register Address 43h (Default = 00h PDN OBUF 0 Register Address 4Ah (Default = 00h Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 LVDS SWING PERF 0 0 MODE 2 ...

  • Page 26

    ... Bits[3:0] Always write '0' 26 Submit Documentation Feedback Register Address BFh (Default = 00h — — — Product Folder Link(s): ADS41B25 www.ti.com PEDESTAL 7LSB 6LSB 5LSB — 0LSB — –1LSB –2LSB — ...

  • Page 27

    ... Copyright © 2011, Texas Instruments Incorporated Register Address CFh (Default = 00h OFFSET CORR TIME CONSTANT TIME CONSTANT (Number of Clock Cycles) Register Address DFh (Default = 00h LOW SPEED 0 Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 OFFSET 16M 32M ...

  • Page 28

    ... SFDR = 71.2dBc SINAD = 66dBFS SNR = 67.2dBFS −20 THD = 70.9dBc −40 −60 −80 −100 −120 Product Folder Link(s): ADS41B25 www.ti.com FFT FOR 70MHz INPUT SIGNAL Frequency (MHz) Figure 13. FFT FOR 300MHz INPUT SIGNAL ...

  • Page 29

    ... Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 FFT FOR TWO-TONE INPUT SIGNAL Each Tone at −36dBFS Amplitude f =100.1MHz IN1 f =105.1MHz IN2 TwoTone IMD = 94.9dBFS SFDR = 100.4dBFS Frequency (MHz) Figure 17 ...

  • Page 30

    ... SFDR(dBc SFDR(dBFS) SNR 66.5 20 −5 0 −50 −45 −40 −35 −30 −25 −20 −15 −10 Product Folder Link(s): ADS41B25 www.ti.com 150MHz 300MHz 170MHz 400MHz 220MHz 1 1.5 2 2.5 3 3.5 Digital Gain (dB) Figure 21. 71 Input Frequency = 170MHz 70.5 70 69.5 69 68.5 68 67.5 SFDR(dBc) 67 ...

  • Page 31

    ... PERFORMANCE vs DRVDD SUPPLY VOLTAGE 92 AVDD = 1.85 AVDD = 1.9 AVDD = 1. 1.65 1.7 1. Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 AVDD = 1.65 AVDD = 1.85 AVDD = 1.7 AVDD = 1.9 AVDD = 1.75 AVDD = 1.95 AVDD = 1.8 Input Frequency = 70MHz Temperature (°C) Figure 25. 70.5 SFDR SNR 70 69 ...

  • Page 32

    ... Input Common−Mode Voltage (1.7V) 69.5 −10 69 −20 68.5 −30 68 −40 67.5 − −60 0 Frequency of Input Common−Mode Signal (MHz) Product Folder Link(s): ADS41B25 www.ti.com 70 SFDR SNR 69.5 69 68.5 68 67.5 Input Frequency = 70MHz 67 Differential Clock Amplitude ( Figure 29. CMRR vs FREQUENCY Signal Superimposed PP 50 ...

  • Page 33

    ... IN - PSRR - 170 150 130 110 Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 PSRR vs FREQUENCY PSRR on AVDD Supply 50mV PP PSRR on AVDD_BUF Supply 100mV Frequency of Signal on Supply (MHz) Figure 33. POWER vs SAMPLING FREQUENCY Analog Power (AVDD Power + BUF Power) ...

  • Page 34

    ... FFT, unless otherwise noted. 34 Submit Documentation Feedback DRVDD CURRENT vs SAMPLING FREQUENCY 60 LVDS 350mV Swing LVDS 200mV Swing CMOS Default 100 Sampling Speed (MSPS) Figure 36. Product Folder Link(s): ADS41B25 www.ti.com 125 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 35

    ... In put ncy (MHz SFDR (dBc) Figure 38. Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 300 350 400 300 ...

  • Page 36

    ... ncy (MHz SNR (dBFS) Figure 39. SNR CONTOUR (3.5dB Gain) 66.2 66 65.8 66.2 66 65.8 65.8 66.2 66 100 150 200 250 In put ncy (MHz) 63.5 64 64.5 65 SNR (dBFS) Figure 40. Product Folder Link(s): ADS41B25 www.ti.com 67.5 67 66.5 66 65.5 66 65.5 67 66 300 350 400 67 68 65.3 64.8 64.3 64.8 65.3 64.3 64.8 63.8 64.3 63.3 65 ...

  • Page 37

    ... THEORY OF OPERATION The ADS41B25 is a buffered analog input and ultralow power ADC with maximum sampling rates up to 125MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block ...

  • Page 38

    ... Simulation IN R Measurement IN 0 0.1 0.2 0.3 0.4 0.5 Frequency (GHz) ) Across Frequency Simulation IN C Measurement 0.1 0.2 0.3 0.4 0.5 Frequency (GHz) ) Across Frequency IN Product Folder Link(s): ADS41B25 www.ti.com ) seen by looking into the ADC input IN 0.6 0.7 0.6 0.7 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 39

    ... Figure 44 and Figure 5W INP T1 25W 0 25W INM 1 50W 50W 0 50W 50W 1:1 5W Figure 44 and Figure Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 45—one optimized for low input INP INM 45. The center point of this termination Submit Documentation Feedback 39 ...

  • Page 40

    ... SBAS548 – JUNE 2011 CLOCK INPUT The ADS41B25 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources ...

  • Page 41

    ... OFFSET CORRECTION The ADS41B25 has an internal offset corretion algorithm that estimates and corrects dc offset up to ±10mV. The correction can be enabled using the EN OFFSET CORR serial register bit. Once enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency ...

  • Page 42

    ... Figure 49. Time Response of Offset Correction POWER DOWN The ADS41B25 has three power-down modes: power-down global, standby, and output buffer disable. Power-Down Global In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down, resulting in reduced total power dissipation of about 7mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100µ ...

  • Page 43

    ... DIGITAL OUTPUT INFORMATION The ADS41B25 provides 12-bit data and an output clock synchronized with the data. Output Interface Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin. ...

  • Page 44

    ... CLKOUTM D0_D1_P , D0_D1_M D2_D3_P , D2_D3_M D4_D5_P , D4_D5_M D6_D7_P , D6_D7_M D8_D9_P , D8_D9_M D10 D11 D10 Sample N Sample Figure 51. DDR LVDS Interface Product Folder Link(s): ADS41B25 www.ti.com D11 Copyright © 2011, Texas Instruments Incorporated ...

  • Page 45

    ... After reset, the buffer presents an High Low OUTP OUTM High Low = 100Ω). To match with a 50Ω external termination, set the OUT Figure 54. Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 External 100 Load W R OUT Figure 53 depicts the CMOS Submit Documentation Feedback 45 ...

  • Page 46

    ... ADS41B25 SBAS548 – JUNE 2011 46 Submit Documentation Feedback Pins OVR CLKOUT 12-Bit ADC Data D9 D10 D11 ADS41B25 Figure 53. CMOS Output Interface Product Folder Link(s): ADS41B25 www.ti.com Copyright © 2011, Texas Instruments Incorporated ...

  • Page 47

    ... Receiver (FPGA, ASIC, etc.) Flip-Flops CLKOUT CLKIN D0 D0_In D1 D1_In D2 D2_In D10 D10_In D11 D11_In Use short traces between ADC output and receiver pins ( inches). × DRVDD × (N × AVG Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 (1) Submit Documentation Feedback 47 ...

  • Page 48

    ... Supply Decoupling Because the ADS41B25 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Note that decoupling capacitors can help filter external power-supply noise, so the optimum number of capacitors depends on the actual application. The decoupling capacitors should be placed very close to the converter supply pins ...

  • Page 49

    ... calculated by dividing the maximum deviation MIN MAX – T range by the difference T MAX MAX ) and distortion (P N Product Folder Link(s): ADS41B25 ADS41B25 SBAS548 – JUNE 2011 . 0.5/100 ideal ideal . MIN ) to the noise floor power ( the power S ), but excluding dc. ...

  • Page 50

    ... It is typically expressed in dBc. 50 Submit Documentation Feedback is the change in supply voltage and ΔV is the change in the common-mode voltage of the input pins and ΔV Product Folder Link(s): ADS41B25 www.ti.com ( the power of the S (5) – – ...

  • Page 51

    ... Orderable Device (1) Package Type Package Status ADS41B25IRGZR ACTIVE VQFN ADS41B25IRGZT ACTIVE VQFN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. ...

  • Page 52

    ... TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Type Drawing ADS41B25IRGZR VQFN RGZ ADS41B25IRGZT VQFN RGZ PACKAGE MATERIALS INFORMATION Pins SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 48 2500 330.0 16.4 7.3 48 250 330.0 16.4 7.3 Pack Materials-Page 1 16-Feb-2012 Pin1 ...

  • Page 53

    ... Device Package Type ADS41B25IRGZR VQFN ADS41B25IRGZT VQFN PACKAGE MATERIALS INFORMATION Package Drawing Pins SPQ Length (mm) RGZ 48 2500 RGZ 48 250 Pack Materials-Page 2 16-Feb-2012 Width (mm) Height (mm) 336.6 336.6 28.6 336.6 336.6 28.6 ...

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  • Page 57

    ... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’ ...